CS4228A-KS Cirrus Logic, CS4228A-KS Datasheet - Page 18

• Manufacturer Part Number: CS4228A-KS
• Description: 24-Bit/ 96 kHz Surround Sound Codec
• Manufacturer: Cirrus Logic

Since the read operation can not set the MAP, an
aborted write operation is used as a preamble. As
shown in Figure 15, the write operation is aborted
after the acknowledge for the MAP byte by sending
a stop condition. The following pseudocode illus-
trates an aborted write operation followed by a read
operation.
18
SCL
SD A
Send start condition.
Send 001000x0 chip address & write operation.
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 001000x1 chip address & read operation.
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
SDA
SCL
ST AR T
START
0
0
CH IP AD D RE SS (W RITE)
0
0
1
0
CHIP ADDRESS (WRITE)
1
1
2
0
0
1
3
2
0 A D 1 AD 0 0
0
4
3
5
0 AD1 AD0 0
4
Figure 15. Control Port Timing, Two Wire Slave Mode Read
Figure 14. Control Port Timing, Two Wire Slave Mode Write
6
5
7
6
A CK
8
7
9
IN CR
ACK
8
10 1 1
6
INCR
9
5
M A P BY TE
10 11
12 13
6
4
MAP BYTE
5
3
12
14 15
4
2
13 14 15
1
3
16
0
2
AC K
S TO P
1 7 1 8
1
S TAR T
16 17 18
0
ACK
Setting the auto increment bit in the MAP allows
successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.
3.8 Control Port Bit Definitions
All registers are read/write, except the Chip Status
register which is read-only. For more detailed in-
formation, see the bit definition tables.
3.9 Power-up/Reset/Power Down Mode
Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers are reset to their default
settings, and the device remains in a low power
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re-
set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.
1 9
0
7
20 21
C HIP A DD R ES S (R EA D)
0
19
1
6
DATA
0
22 2 3 2 4
24 25
1
0 AD 1 A D 0 1
0
ACK
26
25
27 28
26 27
7
A CK
DATA +1
6
28
7
D A TA
1
0
0
A C K
D ATA +1
7
7
DATA +n
6
0
1
CS4228A
DA TA + n
0
7
ACK
DS511PP1
STOP
0
AC K
N O
STO P