cs4228-ks Cirrus Logic, Inc., cs4228-ks Datasheet

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cs4228-ks

Manufacturer Part Number
cs4228-ks
Description
24-bit, Surround Sound Codec
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS4228-KS
Manufacturer:
CRYSTAL
Quantity:
20 000
Part Number:
cs4228-ksZ
Manufacturer:
CIRRUS
Quantity:
20 000
Features
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Advance Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Two 24-bit A/D Converters
- 102 dB dynamic range
- 90 dB THD+N
Six 24-bit D/A Converters
- 103 dB dynamic range and SNR
- 90 dB THD+N
Sample rates up to 100 kHz
Pop-free Digital Output Volume Controls
- 90.5 dB range, 0.5 dB resolution (182 levels)
- Variable smooth ramp rate, 0.125 dB steps
Mute Control pin for off-chip muting circuits
On-chip Anti-alias and Output Filters
De-emphasis filters for 32, 44.1 and 48 kHz
I
SDOUT
SDIN1
SDIN2
SDIN3
LRCK
SCLK
24-Bit, 96 kHz Surround Sound Codec
SCL/CCLK
CLOCK MANAGER
MCLK
CONTROL PORT
SDA/CDIN
AD0/CS
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
DIGITAL VOLUME
DIGITAL VOLUME
DIGITAL VOLUME
DIGITAL VOLUME
DIGITAL VOLUME
DIGITAL VOLUME
Copyright
MUTE CONTROL
Description
The CS4228 codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, along with
volume controls, in a compact +5/+3.3 V, 28-pin SSOP
device. Combined with an IEC958 (SPDIF) receiver (like
the CS8414) and surround sound decoder (such as one
of the CS492x or CS493xx families), it is ideal for use in
DVD player, A/V receiver and car audio systems sup-
porting multiple standards such as Dolby Digital AC-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.
A flexible serial audio interface allows operation in Left
Justified, Right Justified, I
ORDERING INFORMATION
(All Rights Reserved)
MUTEC
CS4228-KS
CDB4228
Cirrus Logic, Inc. 1999
DAC #1
DAC #2
DAC #3
DAC #4
DAC #5
DAC #6
RST
-10° to +70° C 28-pin SSOP
RIGHT ADC
LEFT ADC
DGND
DGND
2
VD
S, or One Line Data modes.
VL
AGND
AGND
VA
CS4228
Evaluation Board
FILT
AOUT1
AOUT2
AOUT3
AINL+
AINL-
AINR+
AINR-
AOUT5
AOUT6
AOUT4
DS307PP1
JUL ‘99
1

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cs4228-ks Summary of contents

Page 1

... DVD player, A/V receiver and car audio systems sup- porting multiple standards such as Dolby Digital AC-3, AAC, DTS, Dolby ProLogic, THX, and MPEG. A flexible serial audio interface allows operation in Left Justified, Right Justified, I ORDERING INFORMATION CS4228-KS CDB4228 RST AD0/CS MUTEC MUTE CONTROL DIGITAL VOLUME ...

Page 2

... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4228 DS307PP1 ...

Page 3

... Figure 8. Butterworth Output Filter with Mute .......................................................... 13 Figure 9. Right Justified Serial Audio Formats ........................................................ 15 2 Figure 10.I S Serial Audio Formats .......................................................................... 15 Figure 11.Left Justified Serial Audio Formats .......................................................... 15 Figure 12.One Line Data Serial Audio Format ......................................................... 16 Figure 13.Control Port Timing, SPI mode ................................................................ 17 Figure 14.Control Port Timing, I DS307PP1 2 C Mode ................................................................. 17 CS4228 3 ...

Page 4

... Typ Max Min Typ Max - 0.003 - 102 - TBD 102 - 99 - TBD 99 - -90 TBD - -90 TBD 0 0 5.66 5.66 100 - - 100 - - - 20 0.05 - 5617 66.53 - 5578 - - 15 CS4228 Units Bits % LSB Vp-p ppm/° kHz dB kHz Degree dB DS307PP1 ...

Page 5

... THD - 0.003 THD TBD (All Outputs) TBD -90.5 - TBD - 100 - - 100 ±0.1 - ±0.5 0 (Notes (Note 6) 24.1 (Notes (Notes 4, 7) tgd - 16/Fs CCIR-2K - TBD CS4228 High Rate Mode Max Min Typ Max - TBD 103 - - - 103 - - - 100 - - - 0.003 - -90 TBD - - 0 ...

Page 6

... (Digital Inputs 25° +3.3V +5V, outputs loaded with A Symbol Fs BRM HRM BRM MCLK =128, 384 Fs MCLK = 256, 512 Fs HRM MCLK = 64, 192 Fs MCLK = 128, 256 Fs CS4228 Typ Max Min Typ Max 25 TBD - 25 TBD 2 TBD - 2 TBD 42 TBD - 48 TBD TBD ...

Page 7

... Slave Mode SCLK Period SCLK High Time SCLK Low Time SCLK rising to LRCK Edge LRCK Edge to SCLK Rising Notes: 8. After powering up the CS4228, RST should be held low until the power supplies and clocks are settled. SCLK* (output) LRCK (output) SDOUT Figure 1. Serial Audio Port Master Mode Timing ...

Page 8

... Figure 3. SPI Control Port Timing (TA = 25° +3.3V, Min Max sck t 1.0 csh t 20 css t 66 scl t 66 sch t 40 dsu 100 r2 t 100 f2 t csh CS4228 Units MHz DS307PP1 ...

Page 9

... Repeated Start t high t t sud t sust hdd 2 Figure Control Port Timing CS4228 (T = 25° +3.3V, A Min Max - 100 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4 registered trademark of Philips Stop susp hdst t r Units ...

Page 10

... Symbol Min VD -0.3 Digital VA -0.3 Analog VL -0.3 Interface - (Note 13) -0.7 (Note 14) -0.7 (Note 14) -55 (Power Applied) -65 (AGND, DGND = 0 V, all voltages with respect Symbol Min VD TBD Digital VA 4.75 Analog VL 2.7 Interface T -10 A CS4228 Typ Max Units - ± +125 °C - +150 °C Typ Max Units 3.3 TBD V 5.0 5 ...

Page 11

... FILTER 25 ANALOG AOUT4 FILTER 26 ANALOG AOUT5 FILTER 27 ANALOG AOUT6 FILTER 28 MUTEC 15 50 LRCK 6 50 SCLK 5 SDIN1 Digital Audio 3 SDIN2 Peripheral 2 or SDIN3 DSP 1 SDOUT MCLK * Required for I C control port mode 10 only External Clock Input CS4228 +3. Supply 2 11 ...

Page 12

... FUNCTIONAL DESCRIPTION Overview The CS4228 is a 24-bit audio codec comprised of 2 analog-to-digital converters (ADC) and 6 digital- to-analog converters (DAC), all implemented us- ing single-bit delta-sigma techniques. Other func- tions integrated with the codec include independent digital volume controls for each DAC, digital DAC ...

Page 13

... DAC in- puts. To prevent large transients on the output desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin in the Pin Descriptions section for more informa- tion. Hard Mute is controlled CS4228 by the 13 ...

Page 14

... The Left/Right clock (LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS4228 (master mode may be generated by an exter- nal source (slave mode). The frequency of LRCK is the same as the system sample rate, Fs. ...

Page 15

... Notes 48 Fs Slave only 48 Fs Slave only 48 Fs Slave only Right Channel MSB - LSB Notes 48 Fs Slave only 48 Fs Slave only Right Channel MSB - LSB CS4228 15 ...

Page 16

... I C Mode after a reset. SPI Mode In SPI mode the CS4228 chip select signal, CCLK is the control port bit clock input, and CDIN is the input data line. There is no data output line, therefore all registers are write-only in SPI mode. ...

Page 17

... DIGPDN bit which time the CODEC powers up and normal operation begins. The CS4228 will enter a stand-by mode if the mas- ter clock source stops for approximately the number of MCLK cycles per LRCK period var- ies by more than 32. Should this occur, the control registers retain their settings ...

Page 18

... Decoupling capacitors should be mounted in such a way as to minimize the circuit path length from the CS4228 supply pin, through the capacitor, to the applicable CS4228 AGND or DGND pin. The small value ceramic capacitors should be closest to the part. In some cases, ferrite beads in the VL, VD ...

Page 19

... Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs) CI1 DS307PP1 MAP4 MAP3 CI1 BRM (Fs) HRM (Fs) 128 64 256 128 384 192 512 256 CS4228 MAP2 MAP1 MAP0 CI0 RESERVED ...

Page 20

... ADC data Freeze. The DC offset average is frozen at the current value and subtracted from incoming ADC data. Allows passthru of DC information ADCPDN DACPDN56 HPF HPFZ CS4228 DACPDN34 DACPDN12 RESERVED RESERVED DS307PP1 ...

Page 21

... DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg- isters before asserting HMUTE Normal operation 1 - DAC pair is muted DS307PP1 MUT4 MUT3 MUT2 RESERVED HMUTE56 CS4228 2 1 MUT1 RMP1 RMP0 HMUTE34 HMUTE12 RESERVED ...

Page 22

... RMP1:0 in the DAC Volume Control Setup register 181 represents attenuation in 0.5 dB steps DEM6 DEM5 DEM4 VOLn CS4228 DEM3 DEM2 DEM1 DS307PP1 ...

Page 23

... No overflow 1 - ADC overflow has occurred DS307PP1 DMS1 DMS0 RESERVED BRM (Fs) HRM (Fs) 32 (1) 16 (3) 48 (2) 24 (4) *64 32 (1) 128 modes 2 S, External Slave mode only DDF2 DDF1 RESERVED 0 0 CS4228 0 DFF0 ...

Page 24

... AINR AD0/CS AINR RST MUTEC 14 15 CS4228 Analog Output 6 Analog Output 5 Analog Output 4 Analog Output 3 Analog Output 2 Analog Output 1 Analog Ground Analog Power Left Channel Analog Input+ Left Channel Analog Input- Internal Voltage Filter Right Channel Analog Input- ...

Page 25

... Digital Ground - DGND Pin 7, Inputs Function: Digital ground reference. Digital Power - VD Pin 8, Input Function: Digital power supply. Typically 3.3 VDC. Digital Interface Power - VL Pin 9, Input Function: Digital interface power supply. Typically 3.3 or 5.0 VDC. All digital output voltages and input thresholds scale with VL. DS307PP1 CS4228 25 ...

Page 26

... When high, the control port and the CODEC become operational. 26 MCLK (MHz) HRM 192x 256x 128x - - 4.0960 - - 5.6448 - - 6.1440 12.2880 16.3840 16.9344 22.5792 18.4320 24.5760 Table 2. Common Master Clock Frequencies CS4228 BRM 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 - - - - - - - - - 512x 16.3840 22.5792 24.5760 ...

Page 27

... Analog Output - AOUT1, AOUT2, AOUT3, AOUT4, AOUT5 and AOUT6 Pins 23, 24, 25, 26, 27, 28, Outputs Function: Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers VOL6 - VOL1. DS307PP1 CS4228 27 ...

Page 28

... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid- scale input code. Units are in volts. 28 CS4228 DS307PP1 ...

Page 29

... DS307PP1 SEATING PLANE SIDE VIEW INCHES MIN MAX -- 0.084 0.002 0.010 0.064 0.074 0.009 0.015 0.390 0.413 0.291 0.323 0.197 0.220 0.022 0.030 0.025 0.041 0° 8° CS4228 1 E1 END VIEW L MILLIMETERS NOTE MIN MAX -- 2.13 0.05 0.25 1.62 1.88 0.22 0.38 2,3 9.90 10.50 1 7.40 8.20 5.00 5.60 1 0.55 0.75 0.63 1.03 0° 8° 29 ...

Page 30

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