CS4228A-KSR Cirrus Logic, Inc., CS4228A-KSR Datasheet
CS4228A-KSR
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CS4228A-KSR Summary of contents
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... CLOCK MANAGER MCLK www.cirrus.com Description The CS4228A codec provides two analog-to-digital and six digital-to-analog Delta-Sigma converters, along with volume controls compact 28-pin SSOP device. Combined with an IEC958 (SPDIF) receiver (like the CS8414) and surround sound decoder (such as one of ...
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... DTS is a registered trademark of the Digital Theater Systems, Inc. Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc. THX is a registered trademark of Lucasfilms Ltd Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys 2 C system. CS4228A ...
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... Figure 14. Control Port Timing, SPI Slave Mode Write................................................................. 18 Figure 15. Control Port Timing, I2C Slave Mode Write ................................................................. 19 Figure 16. Control Port Timing, I2C Slave Mode Read................................................................. 19 LIST OF TABLES Table 1. Serial Audio Port Input Channel Allocations ................................................................... 16 Table 2. User Registers ................................................................................................................ 21 Table 3. Common Master Clock Frequencies.............................................................................. 27 CS4228A 3 ...
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... DGND = 0V; all voltages with respect to Symbol Digital VD Analog VA Interface (Note 12) (-KS (AGND, DGND = 0 V, all voltages with respect to ground.) Symbol Digital VD Analog VA Interface (Note 1) (Note 2) Input Pins (Power Applied) CS4228A = 25° 5.0V 5.0V) A Min Typ Max Units 4.75 5.0 5.25 V 4.75 5.0 5.25 V 3. 2. ° ...
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... Input test signal is a Base Rate Mode Symbol Min (A weighted) 91 (unweighted) (Note 4) THD 5. (Note 5) 0.022 - (Note 5) 30.0 (Note 17/Fs gd ∆ (Note 7) - -0. CS4228A = 10 kΩ pF High Rate Mode Typ Max Min Typ Max -88 -83 - -88 -83 100 - - 100 - 0 0 ...
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... Digital filter characteristics. 10. Measurement bandwidth Fs. 6 (Continued) Base Rate Mode Symbol Min (A weighted) 93 (unweighted 3. (Notes (Note 9) - (Notes 8, 9) 26.2 (Notes 8, 10) 70 tgd - 29/Fs CCIR-2K - CS4228A High Rate Mode Typ Max Min Typ Max 100 - 93 100 - -90 -83 - - ...
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... VL=3. -2 -100 µ -2 2 100 µ -2 (Digital Inputs) CS4228A Min Typ Max Units - 105 0.2 0 567 715 12 °C/Watt ...
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... LRCK Edge to SCLK Rising Notes: 14. See Cl1:0 register on page 22 for settings. 15. After powering up the CS4228A, RST should be held low for 1 ms after the power supplies and clocks are settled. 16. Scales with sample rate Fs valid at 48 kHz, more time at slower Fs and less time at faster Fs. ...
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... Figure 2. Serial Audio Port Slave Mode Timing CS4228A 9 ...
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... MHz SCK Symbol (Note 18) (Note 19) (Note 19) t css t scl dsu Figure 3. SPI Control Port Timing CS4228A (Inputs: Logic 0 = 0V, Logic 1 = VL) Min Max sck t 1.0 csh t 20 css t 66 scl t ...
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... This issue can be worked around by placing a Schmitt Trigger buffer, for example a 74VHC14, on the SCL line just prior to the CS4228A. See Figure 5. This will not affect the operation of the bus in either mode, as pin input only. ...
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... C S4228A AIN R + FILT L 0 ote and pin s should both be tied to a com m on ground p lane. CS4228A V L Ferrite B ead + upply µ µ 0 ...
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... FUNCTIONAL DESCRIPTION 3.1 Overview The CS4228A is a 24-bit audio codec comprised of 2 analog-to-digital converters (ADC) and 6 digital- to-analog converters (DAC), all implemented us- ing single-bit delta-sigma techniques. Other func- tions integrated with the codec include independent digital volume controls for each DAC, digital DAC ...
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... DC. 3.3 Analog Outputs 3.3.1 Line Level Outputs The CS4228A contains on-chip buffer amplifiers capable of producing line level outputs. These am- plifiers are biased to a quiescent DC level of ap- proximately 2.3V. This bias, as well as variations in offset voltage, are removed using off-chip AC load coupling ...
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... The Left/Right clock (LRCK) is used to indicate left and right data frames and the start of a new sample period. It may be an output of the CS4228A (master mode may be generated by an exter- nal source (slave mode). The frequency of LRCK is the same as the system sample rate, Fs. ...
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... BRM available in slave mode only 32 HRM 48, 64, 128 Fs BRM available in slave mode only 64 Fs HRM Figure 11. Left Justified Serial Audio Formats CS4228A Serial Audio Interface Formats ...
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... LSB MSB DAC3 DAC5 DAC2 20 clks 20 clks 20 clks ADCR 20 clks SCLK Rate(s) Notes 128 Fs 6 inputs, 2 outputs, BRM only CS4228A Right Channel clks Right Channel LSB MSB LSB MSB DAC4 DAC6 20 clks 20 clks ...
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... All other transitions of SDA occur while the clock is low. The first byte sent to the CS4228A after a Start con- dition consists bit chip address field and a R/W bit (high for a read, low for a write). The AD0 pin determines the LSB of the chip address field ...
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... CODEC are in re- set, but the control port is active and the desired register settings can be loaded. Normal operation is achieved by setting the DIGPDN bit which time the CODEC powers up and normal operation begins. CS4228A DATA +1 DATA +n ...
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... CS4228A. Both capacitors on the FILT pin should be as close to the CS4228A as possible. Any noise that couples onto the FILT pin will couple directly onto all of the analog outputs. Please see the CDB4228 evalu- ation board data sheet for recommended layout of the decoupling components ...
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... Vol6 Vol5 Vol4 Vol6 Vol5 Vol4 DCK0 DMS1 DMS0 ADCOVL Reserved Reserved Table 2. User Registers CS4228A MAP3 MAP2 MAP1 CI1 CI0 Reserved Reserved Reserved Reserved MUT2 MUT1 RMP1 1 ...
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... ADC power down MAP4 MAP3 CI1 BRM (Fs) HRM (Fs) 128 64 256 128 384 192 512 256 ADCPDN DACPDN56 CS4228A MAP2 MAP1 MAP0 CI0 RESERVED DACPDN34 DACPDN12 RESERVED ...
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... RMP1:0 Attenuation ramp rate 0.5 dB change per 4 LRCKs 1 - 0.5 dB change per 8 LRCKs 2 - 0.5 dB change per 16 LRCKs 3 - 0.5 dB change per 32 LRCKs HPF HPFZ MUT4 MUT3 MUT2 CS4228A RESERVED MUT1 RMP1 RMP0 ...
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... RMP1:0 in the DAC Volume Control Setup register 181 represents attenuation in 0.5 dB steps RESERVED HMUTE56 DEM6 DEM5 DEM4 VOLn CS4228A 2 1 HMUTE34 HMUTE12 RESERVED DEM3 DEM2 DEM1 ...
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... ADC overflow bit, read only overflow 1 - ADC overflow has occurred DMS1 DMS0 RESERVED BRM (Fs) HRM (Fs) 32 (1) (3) 48 (2) (3) *64 32 (1) 128 compatible, maximum 24-bit CS4228A 2 1 DDF2 DDF1 RESERVED DFF0 ...
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... MCLK. The required relationship between the Left/Right clock, serial clock and serial audio data is defined by the Serial Port Mode register. The options are detailed in Figures 10, 11, 12 and 13. CS4228A SUB Analog Out #6,Subwoofer CENTER Analog Out #5, Center ...
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... DAC outputs, and to prevent the clicks and pops that can occur in any single supply system. Use of the Mute Control pin is not man- datory but recommended. CS4228A MCLK (MHz) BRM 256x ...
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... Analog Power (Input) - Power for the analog and reference circuits. Analog Ground (Input) - Analog ground reference. Analog Outputs (Output) - Analog outputs from the DACs. The full scale analog output level is specified in the Analog Characteristics specifications table. The amplitude of the outputs is controlled by the Digital Volume Control registers 0x07 - 0x0C. CS4228A ...
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... Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. CS4228A 29 ...
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... The change in gain value with temperature. Units in ppm/°C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid- scale input code. Units are in Volts. 30 CS4228A ...
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... SIDE VIEW NOM MAX MIN -- 0.084 0.006 0.010 0.05 0.069 0.074 1.62 -- 0.015 0.22 0.4015 0.413 9.90 0.307 0.323 7.40 0.209 0.220 5.00 0.026 0.030 0.55 0.0354 0.041 0.63 4° 8° JEDEC #: MO-150 Controlling Dimension is Millimeters CS4228A ∝ END VIEW L PLANE MILLIMETERS NOM MAX -- -- 2.13 0.15 0.25 1.75 1.88 -- 0.38 10.20 10.50 7.80 8.20 5.30 5.60 0.65 0.75 0.90 1.03 0° 4° 8° NOTE ...
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