XE3005 ETC, XE3005 Datasheet - Page 13

• Manufacturer Part Number: XE3005
• Description: (XE3005 / XE3006) Low-Power Audio CODEC
• Manufacturer: ETC

3.1.1
For transmitting and receiving 32 clock cycles in one frame are always required (figure 12 and 13). This is even
the case when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and
microcontroller.
If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be
shortened).
In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the
data is transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.
The figure 14 shows this special LFS mode.
3.2 Register Programming
The control registers define the configuration of the CODEC and define the various modes of operation. During
power-up, all registers will be configured with default values. The control register set consists of 16 registers. A
detailed description is provided chapter 7.
The control registers can be changed in the two following ways:
There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and
MOSI during the power up startup sequence as described in section 2.1.10
Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without
reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely
omitted and the 3 SPI pins can be fixed to ‘0’ or ‘1’.
13
FSYNC
1. Logic values at SPI pins during power-up
BCLK
SDO
SDI
LFS optimization
Value at power up
channel 1, no data
Figure 14: Audio interface timing in LFS mode,17 BLCK cycles, channel 2
MOSI = 0
MOSI = 1
SCK = 0
SCK = 1
SS = 1
SS = 0
-
-
msb
n
n
15
15
n
n
14
14
channel 2, sample n
Influenced bits of registers
Register I(0)=0
Register I(0)=1
Register J(0)=1
Register J(0)=0
Register E(2) = 0
Register E(2) = 1
channel 1, no data
lsb
n
n
0
0
-
-
msb
channel 2, sample n+1
n
n
15
15
n
n
14
14
comments
MCLKDIV division by 1
MCLKDIV division by 2
SFS protocol
LFS protocol
preamplifier gain x5
preamplifier gain x20
Data Sheet
XE3005/XE3006
D0212-116