XE3005 ETC, XE3005 Datasheet
XE3005
Related parts for XE3005
XE3005 Summary of contents
Page 1
... SS SCK XE3005 / XE3006 Low-Power Audio CODEC General Description The XE3005 is an ultra low-power CODEC (Analog to Digital and Digital to Analog Converter) for voice and audio applications. It includes microphone supply, preamplifier, 16-bit ADC, 16-bit DAC, serial audio interface, power management and clock management for the ADC and the DAC. The sampling frequency of the ADC and of the DAC can be adjusted from 4 kHz to 48 kHz ...
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... Sandman™ Function (XE3006) ............................................................................................................. 16 5 Specifications ......................................................................................................................................... 18 5.1 Absolute Maximum Ratings ..................................................................................................................... 18 5.2 Recommended Operating Conditions...................................................................................................... 18 5.3 Electrical Characteristics.......................................................................................................................... 19 6 Application Information ......................................................................................................................... 26 6.1 Application Schematics – XE3006 ........................................................................................................... 26 7 Register Description .............................................................................................................................. 27 7.1 Register Functional Summary.................................................................................................................. 27 7.2 Register Definitions .................................................................................................................................. 28 8 Mechanical Information ......................................................................................................................... 31 8.1 XE3005 package size (TSSOP20)........................................................................................................... 31 8.2 XE3006 Package size (TSSOP24) .......................................................................................................... 32 2 Data Sheet XE3005/XE3006 D0212-116 ...
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... Figure 1: Pin layout of the XE3006 and XE3005 The XE3006 is available in a TSSOP24 package. The XE3005 is available in a TSSOP20 package. Detailed information is found in chapter 8, Mechanical Information. 1.1 Terminal Descriptions XE3005/6 Terminals Type XE3006 XE3005 Name 1 1 MCLK DI 2 ...
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... C has to be changed. The whole ADC chain can be powered-down through register I. 4 DAC ADC Power Amplifier Serial Audio Interface SPI DSP / Microcontroller Digital wireless transmission – Bluetooth™ Voice recognition / speech synthesis Figure 2: typical usage of CODEC Data Sheet XE3005/XE3006 D0212-116 ...
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... VREG11 11 AIN 12 820k 1µF 1µF GND Vcc 4 0.1µ 820k 1µF 1µF GND Data Sheet XE3005/XE3006 (gain is 5) 200 pF (gain is 20) VDD NRESET VSSA VREG16 VREF VSSA VSSD VREG11 AIN 50 pF (gain is 5) 200 pF (gain is 20) D0212-116 ...
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... J. The complete DAC and PA amplifier chain can be powered-down through register Pulse Width Modulator N pwm_in(5:0) bit streams @ 8xFsync @ 256xFsync Figure 5: DAC block diagram pwm_in(5: pwm_in(5: 2/(256 x Fsync) Data Sheet XE3005/XE3006 XE3005/6 VDDPA P N AOUTP Power Amplifier AOUTN P N VSSPA OUTP-OUTN ...
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... The digital loop back mode can be selected through register J. 2.1.5 Operating Frequency A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the MCLK pin may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal frequency (MCLK/div_factor) should not exceed 12.288 MHz. ...
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... When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter has reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10). 8 Serial Audio Interface Decimator modulator Sandman Interface Data Sheet XE3005/XE3006 FSYNC BCLK SDO SMAD D0212-116 ...
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... The above illustration is valid for either the SMAD output as a result of AIN/SDO or for the SMDA output as a function of AOUT/SDI. 9 Reg I, bit 4 Sandman Interface PWM Power DAC amplifier on-time Data Sheet XE3005/XE3006 SMDA VDDPA AOUTP AOUTN VSSPA + reference - reference Time step = 1/fs = 1/FSYNC off-time 10 time D0212-116 ...
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... NRESET to 0V for at least 32 periods of the MCLK. The circuit which forces the NRESET to 0V should be able to sink at least 50 uA periods of the MCLK. After this VDD = 1.8..3.3V VREG16 = 1.6V VREF = 1. 977 ms (MCLK=2.048KHz) main reset Data Sheet XE3005/XE3006 time D0212-116 ...
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... MCLK, BCLK and FSYNC, the power consumption will reach the standby current of typically 16µA. Use the standard procedure for power up (see start-up and initialization procedure) after a hardware power down and apply your registers setup procedure. 11 delay delay counter low drive MCLK buffer XE3005/6 Data Sheet XE3005/XE3006 NRESET D0212-116 ...
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... BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling edge of the BLCK. Each rising edge of the FSYNC indicates the start of a new sample. 12 channel 2, no data - - - lsb channel 2, sample lsb Data Sheet XE3005/XE3006 channel 1, sample n+1 n+1 15 n+1 15 msb channel 1, sample n+1 n n+1 15 msb D0212-116 ...
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... Influenced bits of registers comments Register I(0)=0 MCLKDIV division by 1 Register I(0)=1 MCLKDIV division by 2 Register J(0)=1 SFS protocol Register J(0)=0 LFS protocol Register E( preamplifier gain x5 Register E( preamplifier gain x20 Data Sheet XE3005/XE3006 D0212-116 ...
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... Max t 125 - recover disable master F 0 SCK master 14 1/F sck Figure 15: SPI signal timing Unit Comments clock period of the master clock MCLK master frequency of the master clock MCLK master Data Sheet XE3005/XE3006 t disable … … D0212-116 ...
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... Figure 17: SPI signal timing in write mode msb D(7: msb read data D(7:0) of address A(4: msb D(7:0) msb write data D(7:0) to address A(4:0) Data Sheet XE3005/XE3006 (4:0) lsb lsb lsb A(4:0) lsb lsb lsb D0212-116 ...
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... Data Sheet XE3005/XE3006 Sandman DAC Comments Sandman disable Sandman disable Sandman disable all registers ...
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... Interface (input terminal SDI 0111’1111’1000’0000 = 0xFF00/2 AIN (mV) if gain = 4 0.00 1.10 2.20 M 280 = 10ms, (code = 200). f min scales proportionally with the sampling min Data Sheet XE3005/XE3006 max positive value reference max AIN (mV) if gain = 20 0.00 0.27 0. the minimum min D0212-116 ...
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... Supply voltage, VDD Analog signal peak-to-peak input voltage, AIN (gain = 20x) Analog signal peak-to-peak input voltage, AIN (gain = 5x) Differential output load resistance Master clock frequency ADC or DAC conversion rate Operating free-air temperature Data Sheet XE3005/XE3006 Conditions Min Max -0.3 3.65 -65 150 -20 ...
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... Cin Input capacitor Rin Input resistance VIN – VSSA Eg gain error offset error input noise INL Integral non linearity DNL Differential non linearity 19 Data Sheet XE3005/XE3006 Test Min Typ Conditions IO = -360uA 2 2mA VSSD-0.5 VIH = 3.3 V VIL = 0.6 V Test Conditions Min Pre-amp gain = 5x 72 Vin=250mV (full scale) ¼ ...
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... MCLK = 5 MHz, ADC off, DAC off MCLK = 12.2880 MHz NRESET mode MCLK = 0 Test Conditions Min ADC off, DAC off MCLK = 5 MHz, ADC off, DAC off MCLK = 12.2880 MHz NRESET mode MCLK = 0 Data Sheet XE3005/XE3006 Typ Max Unit 150 s Typ Max Unit 1 ...
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... FSYNC = 20 kHz, no load ADC off, DAC on FSYNC = 20 kHz, no load Test Conditions Min ADC on, DAC on FSYNC = 48 kHz, no load ADC on, DAC off FSYNC = 48 kHz, no load ADC off, DAC on FSYNC = 48 kHz, no load Data Sheet XE3005/XE3006 Typ Max Unit 350 700 A 240 480 A 120 240 ...
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... LFS and 20, 21 for SFS 22 Test Min Conditions 1024 45 T/4 T 10pF T/4 Load T/4 32xFSYNC BCLK T /4 BCLK T /4 BCLK T /4 BCLK T /4 BCLK Data Sheet XE3005/XE3006 Typ Max Unit 5.12 33 MHz MHz MCLK BCLK ns ns D0212-116 ...
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... FSYNC 10 D15 D14 D13 D12 D11 D10 SDI D15 D14 D13 D12 D11 SDO Figure 18: LFS, timing diagram D10 Figure 19: LFS, zoom timing diagram Data Sheet XE3005/XE3006 D0212-116 ...
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... FSYNC D15 D14 D13 D12 D11 SDI D15 D14 D13 D12 D11 SDO Figure 20: SFS, timing diagram D10 D10 Figure 21: SFS zoom timing diagram Data Sheet XE3005/XE3006 D0212-116 ...
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... M1 M0 MISO MOSI Figure 22: Serial Peripheral Interface timing 25 Test Conditions SCK C = 10pF Load Data Sheet XE3005/XE3006 Min Typ Max Unit MCLK/2 MHz 125 SCK SCK SCK 3 D3 ...
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... VSSD VDDPA 10 15 VREG11 AOUTN 11 14 VSSPA AIN 12 13 820k GND rd order LC output Filter Data Sheet XE3005/XE3006 Sandman output Master Clock SPI Serial Audio Interface R L 2µ2F 4µ L=680µH R=56 lowpass filter, Bluetooth™ voice application MCLK = 2.048 MHz, div_factor =1 ...
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... Define Off-time (low byte) of the Sandman™ function Define Off-time (high byte) of the Sandman™ function Define On-time of the Sandman™ function Define reference amplitude for ADC for Sandman™ function Define reference amplitude for DAC for Sandman™ function Data Sheet XE3005/XE3006 D0212-116 ...
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... The registers and J can be used to configure the XE3005 and XE3006 differently than the default setup. The registers are related to the Sandman ...
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... Short Frame Synchronization mode (slave mode). 0: Long Frame Synchronization mode (mode master or slave). The default is depending on the logic value of the pin SCK during startup (see Section 3.2) SCK=0, default will be set to 1 SCK=1, default will be set to 0 Data Sheet XE3005/XE3006 Description D0212-116 ...
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... ADC 7:0 SMAD_REF Register P (7:0) Sandman™ function, address 0x0F reference for DAC 7:0 SMDA _REF 30 Data Sheet XE3005/XE3006 Default Description value 0x00 00000000 Least significant byte of the off-time of the Sandman™ function Default Description value 0x00 00000000 Most significant byte of the off-time of the Sandman™ ...
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... Mechanical Information 8.1 XE3005 package size (TSSOP20 pin 1 index 1 e DIMENSIONS (mm are the original dim ensions) A UNIT max. 0.15 0.95 0.30 mm 1.10 0.25 0.05 0.80 0.19 Plastic thin shrink small outline package; 20 leads; body width 4 ...
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... 0.2 7.9 4.5 6.6 0.75 0.65 1.0 0.1 7.7 4.3 6.2 0.50 Figure 25: TSSOP24 Data Sheet XE3005/XE3006 detail 0.4 0.5 8 0.2 0.13 0.1 o 0.3 0.2 0 D0212-116 ...