MC68HC11KA Motorola, MC68HC11KA Datasheet - Page 46

• Manufacturer Part Number: MC68HC11KA
• Description: 8-Bit Microcontroller
• Manufacturer: Motorola

SPR2, SPR1 and SPR0 — SPI Clock Rate Selects (SPR2 is located in OPT2 register)
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision
Bit 5 — Not implemented
MODF — Mode Fault (Mode fault terminates SPI operation)
Bits [3:0] — Not implemented
46
MOTOROLA
This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this
flag by reading SPSR (with SPIF = 1), then access SPDR data register.
This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear
this flag by reading SPSR (WCOL = 1), then access SPDR.
Always reads zero
Always read zero
SPI is double buffered in, single buffered out.
SPSR —Serial Peripheral Status Register
SPDR —SPI Data
RESET:
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault (SS is pulled low while MSTR = 1)
This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is
transferred in reverse order (LSB first).
SPIF
Bit 7
Bit 7
Bit 7
0
SPR[2:0]
WCOL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6
0
6
6
—
5
0
5
5
E Clock By
NOTE
Divide
MODF
128
16
32
16
64
2
4
8
4
0
4
4
—
3
0
3
3
E = 2 MHz (Baud)
Frequency at
62.5 kHz
31.3 kHz
15.6 kHz
1.0 MHz
500 kHz
125 kHz
250 kHz
125 kHz
—
2
0
2
2
—
1
0
1
1
MC68HC11KA4TS/D
MC68HC11KA4
$002A
$0029
Bit 0
Bit 0
Bit 0
—
0