MC68HC11KA Motorola, MC68HC11KA Datasheet - Page 32

• Manufacturer Part Number: MC68HC11KA
• Description: 8-Bit Microcontroller
• Manufacturer: Motorola

LIRDV — LIR Driven
CWOM — Port C Wired-OR Mode
Bit 5 — Not implemented
IRVNE — Internal Read Visibility/Not E
LSBF — SPI LSB First Enable
SPR2 — SPI Clock (SCK) Rate Select
XDV1, XDV0 — XOUT Clock Divide Select
32
MOTOROLA
Refer to 2 Operating Modes and On-Chip Memory.
Always reads zero
Refer to 2 Operating Modes and On-Chip Memory.
Refer to 8 Serial Peripheral Interface.
Refer to 8 Serial Peripheral Interface.
Refer to 2 Operating Modes and On-Chip Memory.
OPT2 —System Configuration Options 2
PORTA —Port A Data
RESET:
RESET:
And/or:
Alt. Pin
Func.:
0 = Port C operates normally.
1 = Port C outputs are open-drain.
Do not confuse pin function with the electrical state of the pin at reset. All general-
purpose I/O pins configured as inputs at reset are in a high-impedance state and
the contents of port data registers is undefined. In port descriptions, a “U” indicates
this condition. The pin function is mode dependent.
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Oth-
erwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being
cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled,
writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5
has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O, or output com-
pare. Note that even when PA7 is configured as an output, the pin still drives the
pulse accumulator input.
LIRDV
Bit 7
Bit 7
OC1
PA7
PAI
U
0
CWOM
OC2
OC1
PA6
U
6
0
6
OC3
OC1
PA5
—
U
5
0
5
NOTE
NOTE
IRVNE
OC4
OC1
PA4
—
U
4
4
IC4/OC5
LSBF
OC1
PA3
U
3
0
3
SPR2
PA2
IC1
—
U
2
0
2
XDV1
PA1
IC2
—
U
1
0
1
MC68HC11KA4TS/D
MC68HC11KA4
XDV0
Bit 0
Bit 0
PA0
$0038
$0000
IC3
—
U
0