MPC857DSL Motorola, MPC857DSL Datasheet - Page 15

• Manufacturer Part Number: MPC857DSL
• Description: (MPC857 / MPC862) Hardware Specifications
• Manufacturer: Motorola

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
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Each V
supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply
pins drive distinct groups of logic on chip. The V
least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The
capacitor leads and associated printed circuit traces connecting to chip V
than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V
and GND planes.
All output pins on the MPC862/857T/857DSL have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data busses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V
during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
9
The maximum bus speed supported by the MPC862/857T/857DSL is 66 MHz. Higher-speed parts must be
operated in half-speed bus mode (for example, an MPC862/857T/857DSL used at 80MHz must be
configured for a 40 MHz bus). Table 6 shows the period ranges for standard part frequencies.
Table 7 provides the bus operation timing for the MPC862/857T/857DSL at 33 MHz, 40 Mhz, 50 MHz and
66 Mhz.
The timing for the MPC862/857T/857DSL bus shown assumes a 50-pF load for maximum delays and a
0-pF load for minimum delays.
MOTOROLA
Period
Freq
CC
pin on the MPC862/857T/857DSL should be provided with a low-impedance path to the board’s
Layout Practices
Bus Signal Timing
20.00
Min
50 MHz
Table 6. Period Range for Standard Part Frequencies
30.30
MPC862/857T/857DSL Hardware Specifications
Freescale Semiconductor, Inc.
Max
For More Information On This Product,
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs
15.15
Min
Go to: www.freescale.com
66 MHz
CC
30.30
Max
power supply should be bypassed to ground using at
25.00
Min
80 MHz
CC
30.30
Max
and GND should be kept to less
20.00
Min
100 MHz
Layout Practices
30.30
Max
CC
15