SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 28

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 37 mmdiv/mcksel relationship to clocks needed for I
Notes
1. For these combinations the duty factor of the output SCK2 clock is not necessarily 50%. These combinations are
2. This is illegal but possible.
Table 38 Description of the MMAUD register control bits
Note
1. If enabled, data is written to the CDDA interface from a FIFO located in the CDDA register space. If either ‘daen’ = 1
1997 Aug 01
DIVIDER CODE
ATAPI CD-R block encoder/decoder
therefore not recommended.
or ‘iecen’ = 1 (ieccrtl), the interface will become active.
BIT
7
6
5
3
2
1
0
mmdiv
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
0111
rightmode
leftmode
daen
master
NAME
eiaj
(1)
OVERSAMPLE
MULTIMEDIA
CLOCK
1024f
1536f
128f
192f
256f
384f
512f
768f
48f
64f
96f
VALUE
s
s
s
s
s
s
s
s
s
00
01
10
00
01
10
11
11
s
s
0
1
0
1
0
1
mcksel
CD-DA interface is off
CD-DA Interface is on
I
EIAJ16 serial mode
I
I
I
I
I
reserved
I
left channel.
I
I
reserved
2
2
2
2
2
2
2
2
2
S-bus serial mode
S-bus is slave
S-bus is master
S-bus left channel output is left (default)
S-bus left channel output is right
S-bus left channel output is muted
S-bus right channel output is right (default). This is the opposite default to
S-bus right channel output is left
S-bus right channel output is muted
FREQUENCY
11289600
16934400
22579200
33868800
45158400
67737600
2116800
2822400
4233600
5644800
8467200
(Hz)
28
2
S-bus and IEC 958
n = 1
48 BITS PER
1
16
32
2
4
8
(1)
I
SAMPLE
2
S-BUS,
I
2
S-BUS OUTPUT
DESCRIPTION
n = 2
1
16
2
4
8
(1)
n = 1
1.5
64 BITS PER
1
12
16
24
2
3
4
6
8
(1)
SAMPLE
I
(1)
2
S-BUS,
n = 2
1.5
1
12
2
3
4
6
8
(1)
(1)
Objective specification
n = 1
1.5
SAA7391
12
1
2
3
4
6
8
IEC 958
(n = 2)
(1.5)
(1)
(2)
(3)
(4)
(6)
(2)