SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 14

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 5 Generic host controller interface
Table 6 Miscellaneous pins
Table 7 Sub-CPU interface pins
1997 Aug 01
RESET
DD0 to DD7
DD8 to DD15 D8 to D15
DMARQ
DMACK
DA1
DA2
CS0
CRIN
CROUT
I
POR
TEST1 and TEST2
SRST
INT
INT2
SCCLK
RD
WR/R/W
ALE
ref
ATAPI CD-R block encoder/decoder
NAME
ATAPI
SYMBOL
SYMBOL
RESET
D0 to D7
DMACK
DMARQ
DBWR
DBRD
SCSICS
INTERFACE
GENERIC
NAME
sub-CPU reset
sub-CPU interrupt request
output from host interface
sub-CPU interrupt output from
the SAA7391 drive block and
UART
sub-CPU clock out
sub-CPU read enable
sub-CPU write enable/
read/write control
demultiplex enable input for
lower address lines
DESCRIPTION
controller reset output
controller DMA path/controller data and control bus (optional)
controller upper DMA path (optional)
DMA acknowledge to controller
DMA request from controller
DMA bus write to controller
DMA bus read from controller
controller chip select output for sub-CPU read/write cycles
crystal oscillator/clock input
crystal oscillator output
VCO reference current
power-on reset pin
mode control test pins
DESCRIPTION
GENERIC HOST CONTROLLER INTERFACE MEANING
active HIGH reset if XDD7 is pulled LOW during power-on reset;
active LOW reset if XDD7 is pulled HIGH during power-on reset
open-drain sub-processor interrupt from host interface
open-drain sub-processor interrupt from drive and UART
sub-CPU read enable strobe; if grounded permanently, the WR
signal will act as read/write control input
write enable; alternative usage is read/write if RD is held LOW at
all times; WR has priority over RD at all times
while HIGH, the lower address bits are latched from
SCD0 to SCD7; should be used with a Schmitt trigger input to
avoid false latching due to ground bounce on the
8051 microcontroller
14
clock PLL multiplier
COMMENT
COMMENT
Objective specification
SAA7391