SAA7391H Philips Semiconductors, SAA7391H Datasheet - Page 13

• Manufacturer Part Number: SAA7391H
• Description: ATAPI CD-R block encoder/decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 4 ATAPI target mode interface
1997 Aug 01
RESET
DD0 to DD7
DD8 to DD15 ATAPI D8 to D15: these data bits are only used in accesses to the 16-bit data port
DMARQ
DMACK
IOCS16
IORDY
DA0 to DA2
DIOW
DIOR
CS0
CS1
INTRQ
PDIAG
DASP
ATAPI CD-R block encoder/decoder
NAME
ATAPI
ATAPI reset signal: the SAA7391 will not recognize a signal assertion shorter than 20 ns as a valid
reset signal.
ATAPI D0 to D7
DMA request: this signal, used for DMA data transfers between host and device, is asserted by the
SAA7391 when it is ready to transfer data to or from the host. The direction of data transfer is
controlled by DIOR and DIOW.
DMA acknowledge: this signal is used by the host in response to DMARQ to initiate DMA transfers.
This signal may be temporarily negated by the host to suspend the DMA transfer in process.
ATAPI I/O port is a 16-bit open-drain output: during PIO transfer Modes 0, 1 or 2, IOCS16 indicates to
the host system that the 16-bit data port has been addressed and that the device is prepared to send
or receive a 16-bit data word.
ATAPI I/O ready open-drain output: this signal is negated to extend the host transfer cycle of any host
register access (read or write) when the SAA7391 is not ready to respond to a data transfer request.
This signal is only enabled during DIOR/DIOW cycles to the SAA7391. When IORDY is not active, it is
in the high-impedance (undriven) state.
address bus (device address)
ATAPI write strobe: the rising edge of DIOW latches data from the signals, DD0 to DD7 or
DD0 to DD15 into a register or the data port of the SAA7391. The SAA7391 will not act on the data
until it is latched.
ATAPI read strobe: the falling edge of DIOR enables data from a register or data port of the SAA7391
onto the signals, DD0 to DD7 or DD0 to DD15. The rising edge of DIOR latches data at the host and
the host will not act on the data until it is latched.
ATAPI chip select 0 input: this is the chip select signal from the host used to select the ATA command
block registers. This signal is also known as CS1FX.
ATAPI chip select 1 input: this is the chip select signal from the host used to select the ATA control
block registers. This signal is also known as CS3FX.
ATAPI interrupt output: this signal is used to interrupt the host system. INTRQ is asserted only when
the device has a pending interrupt, the device is selected, and the host has cleared the ‘nien’ bit in the
device control register. If the ‘nien’ bit is equal to 1, or the device is not selected, this output is in a
high-impedance state, regardless of the presence or absence of a pending interrupt.
ATAPI passed diagnostics: this signal shall be asserted by device 1 to indicate to device 0 that it has
completed diagnostics.
ATAPI DASP (device active, device 1 present): this is a time-multiplexed signal which indicates that a
device is active, or that device 1 is present. This signal is an open-drain output.
ATAPI MEANING
13
Objective specification
SAA7391