X9241A Xicor, X9241A Datasheet - Page 3

• Manufacturer Part Number: X9241A
• Description: Quad Digitally Controlled Potentiometer (XDCP)
• Manufacturer: Xicor

X9241A
Serial Interface
The X9241A supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9241A will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9241A are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.
The X9241A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9241A will respond with a final acknowledge.
REV 1.1.13 12/09/02
LOW
HIGH
). SDA state changes during
). The X9241A continuously
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Array Description
The X9241A is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V
R
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9241A
this is fixed as 0101[B].
Figure 1. Slave Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241A compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9241A to respond with an acknowledge.
W
) output. Within each individual array only one
0
Device Type
Identifier
1
H
/R
Characteristics subject to change without notice.
0
H
and V
1
L
A3
/R
L
Device Address
inputs).
A2
A1
A0
3 of 18
W
/