ADV7177 Analog Devices, ADV7177 Datasheet - Page 27

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

NTSC PEDESTAL REGISTERS 3–0 (PCE15–0, PCO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit-wide registers are used to set up the NTSC pedestal
on a line-by-line basis in the vertical blanking interval for both
odd and even fields. Figure 40 show the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal OFF on the equivalent line when used in
NTSC.
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
REV. 0
FIELD 1/3
FIELD 2/4
FIELD 1/3
FIELD 2/4
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15
PCE15
PCO7
PCE7
Figure 40. Pedestal Control Registers
PCO14
PCE14
PCO6
PCE6
REG 11
REG 0
REG 1
REG 2
PCO13
PCO5
PCE13
PCE5
OSD
OSD
OSD
OSD
BE WRITTEN TO
ZERO SHOULD
PCO12
PCE12
PCO4
PCE4
THIS BIT
MR37
MR37
INPUT DEFAULT COLOR
MR36
0
1
PCO11
PCO3
PCE11
PCE3
INPUT COLOR
BLACK
MR36
PCO10
PCE10
PCO2
PCE2
MR35
0
1
OSD ENABLE
Cr7
Cr1
PCO1
PCO9
PCE1
PCE9
MR35
Cb0
Figure 41. Mode Register 3
DISABLE
ENABLE
Figure 42. OSD Registers
Y0
BE WRITTEN TO
ZERO SHOULD
PCO0
PCO8
PCE0
PCE8
THIS BIT
MR34
MR34
–27–
MR33-32
0
0
1
1
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Clock Output Select (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz or disabled, depending on the
values of these bits.
OSD Enable (MR35)
A logic one in MR35 will enable the OSD function on the
ADV7177.
Reserved (MR36)
These bits are reserved.
Input Default Color (MR36)
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
OSD REGISTER 0–11
(Address [SR4–SR0] = 12H–1DH)
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb and Cr value, there are four zero added
to give the complete byte for each value loaded internally.
(Y0 = [Y0
Cb
MR33
0
1
0
1
CLOCK CONTROL
0
, 0, 0, 0, 0,], Cr = [Cr
CLOCK OUTPUT OFF
13.5MHz OUTPUT
27MHz OUTPUT
CLOCK OUTPUT OFF
3
MR32
, Y0
MR31
VBI PASSTHROUGH
2
0
1
, Y0
Cb7
Cb1
MR31
Y1
1
DISABLE
ENABLE
, Y0
Cr0
0
3
, 0, 0, 0, 0], Cb = [Cb
(READ ONLY)
, Cr
REV CODE
MR30
MR30
ADV7177/ADV7178
2
, Cr
1
, Cr
0
, 0, 0, 0, 0].)
3
, Cb
2
, Cb
1
,