ADV7177 Analog Devices, ADV7177 Datasheet - Page 25

• Manufacturer Part Number: ADV7177
• Description: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
• Manufacturer: Analog Devices

Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit data.
If an 8-bit input is selected the data will be set up on Pins P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
REV. 0
TR17 TR16
FIELD/VSYNC
REGISTER RESET
TR07
TIMING MODE 1 (MASTER/PAL)
0
0
1
1
DATA ADJUSTMENT
HSYNC TO PIXEL
TIMING
HSYNC
TR07
0
1
0
1
TR17
TR06
0 x T
1 x T
2 x T
3 x T
PIXEL PORT
0
1
CONTROL
PCLK
PCLK
PCLK
PCLK
TR06
8-BIT
16-BIT
TR16
T
LINE 1
B
T
A
TR15 TR14
TR15 TR14
x
x
0
0
1
1
RISING EDGE DELAY
TR05 TR04
HSYNC TO FIELD
TR05
0
0
1
1
(MODE 1 ONLY)
(MODE 2 ONLY)
VSYNC WIDTH
Figure 35. Timing Register 0
TR15
Figure 38. Timing Register 1
0
1
0
1
0
1
LUMA DELAY
0
1
0
1
1 x T
4 x T
16 x T
128 x T
T
T
B
B
TR04
T
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
+ 32 s
TR14
C
PCLK
PCLK
PCLK
PCLK
TR03
–25–
BLACK INPUT
0
1
CONTROL
TR03
TR13 TR12
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
ENABLE
DISABLE
0
0
1
1
TR13
FIELD/VSYNC DELAY
BYTE 0
BYTE 0
Figure 36. Closed Captioning Extended Data Register
HSYNC TO
TR02 TR01
BYTE 1
BYTE 1
0
1
0
1
0
0
1
1
TIMING MODE
Figure 37. Closed Captioning Data Register
TR02
SELECTION
TR12
0 x T
4 x T
8 x T
16 x T
CCD7
CED7
0
1
0
1
T
T
CCD15
CED15
B
PCLK
PCLK
PCLK
C
PCLK
LINE 313
MODE 0
MODE 1
MODE 2
MODE 3
CCD6
CED6
TR01
CED14
CCD14
TR11
TR00
TR11 TR10
0
1
0
0
1
1
CCD5
CED5
MASTER/SLAVE
HSYNC WIDTH
CCD13
CED13
CONTROL
SLAVE TIMING
MASTER TIMING
0
1
0
1
LINE 314
TR00
TR10
CCD4
CED4
ADV7177/ADV7178
1 x T
4 x T
16 x T
128 x T
CCD12
CED12
T
PCLK
PCLK
A
CCD3
CED3
PCLK
PCLK
CCD11
CED11
CCD2
CED2
CCD10
CED10
CCD1
CED1
CCD9
CED9
CCD0
CED0
CCD8
CED8