ADV7177 Analog Devices, ADV7177 Datasheet - Page 17

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ADV7177

Manufacturer Part Number
ADV7177
Description
Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
Manufacturer
Analog Devices
Datasheet

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Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC,
BLANK and FIELD for an odd or even field transition relative to the pixel data.
REV. 0
HSYNC
HSYNC
BLANK
BLANK
FIELD
FIELD
622
309
DISPLAY
DISPLAY
HSYNC
BLANK
FIELD
PIXEL
DATA
623
310
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
624
311
EVEN FIELD
ODD FIELD
NTSC = 16 * CLOCK/2
PAL = 12 * CLOCK/2
625
312
ODD FIELD
EVEN FIELD
313
1
Figure 19. Timing Mode 1 (PAL)
314
2
315
3
VERTICAL BLANK
VERTICAL BLANK
–17–
316
4
317
5
318
6
319
7
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
320
Cb
21
ADV7177/ADV7178
Y
334
22
Cr
Y
DISPLAY
335
23
DISPLAY
336

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