X1227 Xicor, X1227 Datasheet - Page 8

• Manufacturer Part Number: X1227
• Description: Real Time Clock/Calendar/CPU Supervisor with EEPROM
• Manufacturer: Xicor

Figure 3. Watchdog Restart/Time Out
X1227
POWER ON RESET
Application of power to the X1227 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for typically 250ms the circuit releases RESET, allow-
ing the system to begin operation. Recommended slew
rate is between 0.2V/ms and 50V/ms.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
REV 1.1.20 1/13/03
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power up.
CC
RESET
SDA
SCL
exceeds the device V
Start
Note: All inputs are ignored during the active reset period (t
t
RSP
t
RSP
<t
TRIP
WDO
Stop Start
threshold value
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t
RSP
>t
WDO
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of
SDA when the SCL line is high and followed by a stop
bit. The start signal restarts the watchdog timer
counter, resetting the period of the counter back to the
maximum. If another start fails to be detected prior to
the watchdog timer expiration, then the RESET pin
becomes active. In the event that the start signal
occurs during a reset time out period, the start will
have no effect. When using a single START to refresh
watchdog timer, a STOP bit should be followed to reset
the device back to stand-by mode.
LOW VOLTAGE RESET OPERATION
When a power failure occurs, and the voltage to the
part drops below a fixed v
issued to the host microcontroller. The circuitry moni-
tors the V
senses a preset threshold voltage. Power up and
power down waveforms are shown in Figure 4. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
When the low voltage reset signal is active, the operation
of any in progress nonvolatile write cycle is unaffected,
allowing a nonvolatile write to continue as long as possi-
ble (down to the power on reset voltage). The low voltage
reset signal, when active, terminates in progress commu-
nications to the device and prevents new commands, to
reduce the likelihood of data corruption.
CC
t
RST
RST
line with a voltage comparator which
).
Characteristics subject to change without notice.
t
RSP
>t
TRIP
WDO
voltage, a reset pulse is
t
RST
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