X1227 Xicor, X1227 Datasheet - Page 4

• Manufacturer Part Number: X1227
• Description: Real Time Clock/Calendar/CPU Supervisor with EEPROM
• Manufacturer: Xicor

Table 1. Clock/Control Memory Map
X1227
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
REV 1.1.20 1/13/03
Addr.
000D
000C
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
(EEPROM)
(EEPROM)
(EEPROM)
(SRAM)
Control
Alarm1
Alarm0
Status
Type
RTC
DWA1
MOA1
MNA1
DWA0
MOA0
MNA0
Name
YRA1
DTA1
HRA1
SCA1
YRA0
DTA0
HRA0
SCA0
Y2K1
Y2K0
Reg
Y2K
DTR
ATR
DW
MO
MN
INT
YR
DT
HR
SC
SR
BL
EDW1
EMO1
EMN1
EDW0
EMO0
EMN0
EDT1
EHR1
ESC1
EDT0
EHR0
ESC0
BAT
Y23
MIL
BP2
0
0
0
0
0
0
0
0
0
0
7
A1M22
A0M22
A1S22
A0S22
M22
AL1
Y22
S22
BP1
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
A1Y2K21
A0Y2K21
A1M21
A0M21
A1D21
A1H21
A0D21
A0H21
Y2K21
A1S21
A0S21
ATR5
M21
D21
H21
AL0
Y21
S21
BP0
5
0
0
0
0
0
0
0
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A1Y2K20
A0Y2K20
A1M20
A0M20
A1G20
A1D20
A1H20
A0G20
A0D20
A0H20
Y2K20
A1S20
A0S20
ATR4
M20
WD1
Y20
G20
D20
H20
S20
4
0
0
0
0
0
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
– *n = 0 for Alarm 0: N = 1 for Alarm 1
Bit
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
A1Y2K13
A0Y2K13
A1M13
A0M13
Y2K13
A1G13
A1D13
A1H13
A1S13
A0G13
A0D13
A0H13
A0S13
ATR3
WD0
M13
Y13
G13
D13
H13
S13
3
0
0
0
0
0
Unused
A1M12
A0M12
A1G12
A1D12
A1H12
A1S12
A0G12
A0D12
A0H12
A0S12
RWEL
DTR2
ATR2
M12
DY2
G12
D12
H12
S12
DY2
DY2
Y12
2
0
0
0
0
Characteristics subject to change without notice.
A1M11
A0M11
A1G11
A1D11
A1H11
A0G11
A0D11
A0H11
A1S11
A0S11
DTR1
ATR1
WEL
M11
DY1
G11
D11
H11
DY1
DY1
Y11
S11
1
0
0
0
0
0 (optional)
A1Y2K10
A0Y2K10
A1M10
A0M10
A1G10
A1D10
A1H10
A0G10
A0D10
A0H10
Y2K10
A1S10
A0S10
DTR0
RTCF
ATR0
M10
DY0
G10
D10
H10
DY0
DY0
Y10
S10
0
Range
19/20
19/20
19/20
0-99
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
0-6
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