ADF4360-3 Analog Devices, ADF4360-3 Datasheet - Page 7

• Manufacturer Part Number: ADF4360-3
• Description: Integrated Synthesizer and VCO
• Manufacturer: Analog Devices

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Table 4. Pin Functional Descriptions
Pin No.
1
2
3, 8–11, 22
4
5
6
7
12
13
14
15
16
17
18
19
20
21
23
24
Mnemonic
CPGND
AV
AGND
RF
RF
V
V
C
R
C
DGND
REF
CLK
DATA
LE
MUXOUT
DV
CE
CP
SET
VCO
TUNE
C
N
OUT
OUT
DD
DD
IN
A
B
Function
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
Analog Ground. This is the ground return path of the prescaler and VCO.
VCO Output. The output level is programmable from –3 dBm to −12 dBm. See the Output Matching section for
a description of the various output stages.
VCO Complementary Output. The output level is programmable from −3 dBm to −12 dBm. See Output
Matching section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CP
synthesizer. The nominal voltage potential at the R
With R
Internal Compensation Node. This pin must be decoupled to V
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of V
100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
Charge Pump Output. When enabled, this provides ± I
I
CPmax
SET
= 4.7 kΩ, I
=
11
R
SET
.
75
CPmax
RF
RF
CPGND
AGND
AV
OUT
OUT
V
= 2.5 mA.
VCO
DD
A
B
1
2
3
4
5
6
Figure 3. Pin Configuration
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ADF4360-3
PIN 1
IDENTIFIER
(Not to Scale)
TOP VIEW
DD
GND
must have the same value as AV
sets the maximum charge pump output current for the
VCO
CP
SET
DD
to the external loop filter, which in turn drives the internal VCO.
18
17
16
15
14
13
must have the same value as AV
pin is 0.6 V. The relationship between I
must have the same value as DV
DATA
CLK
REF
DGND
C
R
N
SET
IN
VCO
with a 10 µF capacitor.
DD
/2 and a dc equivalent input resistance of
DD
.
DD
DD
.
.
CP
ADF4360-3
and R
SET
is