ADF4360-3 Analog Devices, ADF4360-3 Datasheet
ADF4360-3
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ADF4360-3 Summary of contents
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... Integrated Synthesizer and VCO GENERAL DESCRIPTION The ADF4360 fully integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-3 is designed for a center frequency of 1750 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF out- put of between 800 MHz and 975 MHz ...
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... ADF4360-3 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Functional Descriptions.......................... 7 Typical Performance Characteristics ............................................. 8 Circuit Description........................................................................... 9 Reference Input Section............................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 PFD and Charge Pump................................................................ 9 MUXOUT and Lock Detect...................................................... 10 Input Shift Register..................................................................... 10 ...
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... Into 2.00 VSWR load. −19 dBc typ −37 dBc typ −12/−3 dBm typ Programmable steps. See Table 7 ±3 dB typ For tuned loads, see Output Matching section. 1.25/2.5 V min/max Rev Page ADF4360-3 , unless otherwise noted. = 4.7 kΩ. ≤ 2 ≤ 2 ...
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... ADF4360-3 Parameter 1, 5 NOISE CHARACTERISTICS 8 VCO Phase Noise Performance 9 Synthesizer Phase Noise Floor 10, 11 In-Band Phase Noise 12 RMS Integrated Phase Error Spurious Signals due to PFD Frequency 1 Operating temperature range is: –40°C to +85°C. 2 Guaranteed by design. Sample tested to ensure compliance internally modified to maintain constant loop gain over the frequency range. ...
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... DB1 DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless A MIN MAX Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time ...
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... ADF4360-3 ABSOLUTE MAXIMUM RATINGS Table 25°C, unless otherwise noted. A Parameter AV to GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O Voltage to GND REF to GND IN Operating Temperature Range Maximum Junction Temperature CSP θ Thermal Impedance JA (Paddle Soldered) ...
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... CLK 17 REF 16 IN DGND SET must have the same value must have the same value pin is 0.6 V. The relationship between I CP with a 10 µF capacitor. VCO /2 and a dc equivalent input resistance ADF4360-3 and R is SET ...
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... ADF4360-3 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 1 –80 –90 2 –100 –110 –120 –130 –140 –150 –160 –170 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 4. Open-Loop VCO Phase Noise –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 –120 – ...
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... Rev Page 13-BIT B COUNTER LOAD PRESCALER P/P+1 LOAD 5-BIT A MODULUS COUNTER CONTROL N DIVIDER Figure 11. A and B Counters CLR1 PROGRAMMABLE U3 DELAY ABP1 ABP2 CLR2 DOWN Figure 12. PFD Simplified Schematic and Timing (In Lock) ADF4360-3 TO PFD V P CHARGE PUMP CP CPGND ...
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... DIV2 (DB22) high in the N counter latch). The ADF4360 family contains linearization circuitry to minimize any variation of the product of I Rev Page Control Latch R Counter N Counter (A and B) Test Modes Latch ) and resultant V 1450 1550 1650 1750 1850 1950 2050 FREQUENCY (MHz) , ADF4360-3 TUNE and TUNE ...
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... Another feature of the ADF4360 family is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the Mute-Till-Lock Detect (MTLD) bit in the control latch. BUFFER/ VCO DIVIDE Figure 15. Output Stage ADF4360-3 Rev Page ADF4360 ...
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... ADF4360-3 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed. Table 6. Latch Structure PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ...
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... DIGITAL LOCK DETECT (ACTIVE HIGH DIVIDER OUTPUT DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360-3 CONTROL BITS DB2 DB1 DB0 PC1 C2 (0) C1 (0) CORE POWER LEVEL 5mA 10mA 15mA 20mA DD ...
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... ADF4360-3 Table 8. N Counter Latch DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIV2 CPG B13 B12 B11 B10 DIVSEL B13 B12 B11 (FUNCTION LATCH) ...
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... R13 R12 .......... .......... .......... .......... .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... .......... .......... .......... ADF4360-3 CONTROL BITS DB2 DB1 DB0 R1 C2 (0) C1 (1) DIVIDE RATIO 16380 16381 16382 16383 ...
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... ADF4360-3 CONTROL LATCH With (C2, C1) = (0,0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. Power-Down DB21 (PD2) and DB20 (PD1) provide programmable power- down modes ...
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... MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9). Reserved Bits DB23 to DB22 are spare bits and have been designated as Reserved. They should be programmed to 0. Rev Page ADF4360-3 ...
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... The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-3, which allows levels from −12 dBm to −3 dBm from each output. The RF output is designed to drive a 50 Ω load but must be ac- coupled, as shown in Figure 16 ...
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... FIXED FREQUENCY LO Figure 17 shows the ADF4360-3 used as a fixed frequency LO at 1.8 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360 MHz. Since using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as pos- sible, – ...
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... The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND. OUTPUT MATCHING There are a number of ways to match the output of the ADF4360-3 for optimum operation; the most basic is to use a 50 Ω resistor bypass capacitor of 100 pF is con- VCO nected in series as shown Figure 20 ...
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... Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters Frequency Range 1600 MHz to 1950 MHz 1600 MHz to 1950 MHz 1600 MHz to 1950 MHz Rev Page 0.60 MAX PIN 1 INDICATOR 2.25 BOTTOM 2.10 SQ VIEW 1. 0.25 MIN 2.50 REF Package Option CP-24 CP-24 CP-24 Evaluation Board ADF4360-3 ...
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... ADF4360-3 NOTES Rev Page ...
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... NOTES Rev Page ADF4360-3 ...
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... ADF4360-3 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners ...