AD7701AQ Analog Devices, AD7701AQ Datasheet - Page 6

• Manufacturer Part Number: AD7701AQ
• Description: LC2MOS 16-Bit A/D Converter
• Manufacturer: Analog Devices

AD7701
Figure 1. Load Circuit for Access
Time and Bus Relinquish Time
SDATA
TERMINOLOGY
LINEARITY ERROR
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are Zero-Scale (not to be
confused with Bipolar Zero), a point 0.5 LSB below the first
code transition (000 . . . 000 to 000 . . . 001) and Full-Scale, a
point 1.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full
scale.
DIFFERENTIAL LINEARITY ERROR
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of 1 LSB or less
guarantees monotonicity.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Error is the deviation of the last code
transition (111 . . . 110 to 111 . . . 111) from the ideal (V
–3/2 LSBs). It applies to both positive and negative analog input
ranges and it is expressed in microvolts.
UNIPOLAR OFFSET ERROR
Unipolar Offset Error is the deviation of the first code transition
from the ideal (AGND + 0.5 LSB) when operating in the uni-
polar mode. It is expressed in microvolts.
CLKIN
SCLK
Figure 3. SSC Mode Data Hold
Time
CS
OUTPUT
SDATA
PIN
TO
HI-Z
CS
100pF
t
t
Figure 5. SSC Mode Timing Diagram
6
4
C
L
VALID
DATA
DB15
t
7
t
10
1.6mA
t
I
I OH
200 A
OL
8
t
DB14
5
HI-Z
+
2.1V
Figure 4a. SEC Mode Data Hold Time
Figure 2a. Calibration Control Timing
DB1
SC1, SC2
CAL
SDATA
DB0
CS
t
9
REF
SC1,SC2 VALID
VALID
DATA
HI-Z
HI-Z
t
1
–6–
t
15
BIPOLAR ZERO ERROR
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal (AGND – 0.5 LSB) when
operating in the bipolar mode. It is expressed in microvolts.
BIPOLAR NEGATIVE FULL-SCALE ERROR
This is the deviation of the first code transition from the ideal
(–V
expressed in microvolts.
POSITIVE FULL-SCALE OVERRANGE
Positive Full-Scale Overrange is the amount of overhead avail-
able to handle input voltages greater than +V
noise peaks or excess voltages due to system gain errors in
system calibration routines) without introducing errors due to
overloading the analog modulator or overflowing the digital
filter. It is expressed in millivolts.
NEGATIVE FULL-SCALE OVERRANGE
This is the amount of overhead available to handle voltages
below –V
overflowing the digital filter. Note that the analog input will
accept negative voltage peaks even in the unipolar mode. The
overhead is expressed in millivolts.
t
SDATA
2
HI-Z
DRDY
SCLK
REF
CS
+ 0.5 LSB), when operating in the bipolar mode. It is
t
REF
17
HI-Z
Figure 6. AC Mode Timing Diagram
without overloading the analog modulator or
t
18
SDATA
DRDY
SCLK
Figure 4b. SEC Mode Timing Diagram
START
CS
SLEEP
CLKIN
t
Figure 2b. SLEEP Mode Timing
13
HI-Z
DB8
HIGH BYTE
DB15 DB14
DB9
t
11
t
14
LOW BYTE
t
DB7
12
t
REF
3
STOP 1
( for example,
STOP 2
DB1
t
19
REV. D
DB0
t
HI-Z
16
HI-Z