AD7701AQ Analog Devices, AD7701AQ Datasheet - Page 5

• Manufacturer Part Number: AD7701AQ
• Description: LC2MOS 16-Bit A/D Converter
• Manufacturer: Analog Devices

REV. D
TIMING CHARACTERISTICS
Parameter
f
t
t
t
t
t
SSC Mode
t
t
t
t
t
t
t
SEC Mode
f
t
t
t
t
t
t
AC Mode
t
t
t
NOTES
11
12
13
14
15
16
17
18
19
10
11
CLKIN
SCLK
r
f
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
5
5
Sample tested at +25 C to ensure compliance. All input signals are specified with t
See Figures 1 to 6.
CLKIN Duty Cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7701 is not in SLEEP mode. If no clock is present in this case, the device can
The AD7701 is production tested with f
Specified using 10% and 90% points on waveform of interest.
In order to synchronize several AD7701s together using the SLEEP pin, this specification is met.
t
t
If CS is returned high before all 16 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be as
SDATA is clocked out on the falling edge of the SCLK input.
6
7
8
draw higher current than specified and possibly become uncalibrated.
then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true bus relinquish time of the part and as such as independent of external bus loading capacitance.
great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high sooner than
4 CLKIN cycles plus 160 ns after CS goes low.
4
9
8, 9
7, 10
11
8
8
, t
and t
10
, t
3, 4
13
15
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
and t
16
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is
Limit at T
(A, B Versions)
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
(4/f
5
35
160
160
150
250
200
40
180
200
CLKIN
CLKIN
CLKIN
+200
) +200
MIN
, T
MAX
CLKIN
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
1, 2
Limit at T
(S, T Versions)
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
(4/f
5
35
160
160
150
250
200
40
180
200
CLKIN
CLKIN
CLKIN
(AV
f
CLKIN
DD
+200
) +200
= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
= DV
MIN
DD
, T
= +5 V
MAX
kHz min
MHz max Typically 4.096 MHz
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
MHz
ns min
ns min
ns max
ns max
ns max
ns max
ns min
ns max
ns max
Units
–5–
10%; AV
r
= t
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
SS
Conditions/Comments
Master Clock Frequency: Internal Gate Oscillator
Master Clock Frequency: Externally Supplied
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time After CAL Goes High
SLEEP High to CLKIN High Setup Time
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns
SCLK High Pulse Width. Typically 240 ns
SCLK Low Pulse Width. Typically 730 ns
SCLK Rising Edge to Hi-Z Delay (l/f
CS High to Hi-Z Delay
Serial Clock Input Frequency
SCLK Input High Pulse Width
SCLK Low Pulse Width
Data Access Time (CS Low to Data Valid). Typically 80 ns
SCLK Falling Edge to Data Valid Delay. Typically 75 ns
CS High to Hi-Z Delay
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
CS Setup Time. Typically 20 ns
Data Delay Time. Typically 90 ns
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns
= DV
SS
= –5 V
10%; AGND = DGND = O V;
DD
)
CLKIN
AD7701
+ 100 ns typ)