UPC1830GT NEC, UPC1830GT Datasheet - Page 18

• Manufacturer Part Number: UPC1830GT
• Description: FILTER-CONTAINING VIDEO CHROMA/ SYNCHRONIZING SIGNAL PROCESSING LSI COMPATIBLE WITH NTSC/PAL SYSTEM
• Manufacturer: NEC

(5) G-Y demodulation circuit
(6) RGB matrix circuit
5.4 Synchronizing Signal Processing Section
(1) Input signal
(2) Sync. separation circuit
synchronization peak (minimum potential) becomes approximately 2.5 V. The voltage of the sync. separate
input pin (pin 39) becomes 2.5 V or higher during a period other than the synchronization peak (minimum
potential), thus cutting off transistor TR1 (reducing the collector current of TR1). Consequently, a charge in C
is discharged via R
18
In Figure 5-6, the slice level of sync. separation is determined as follows:
When a negative sync. video signal is input, charge current I
Demodulates G-Y using (R-Y)’, (B-Y)’ which is color difference signal after tint adjustment and the following
expression.
G-Y demodulation expression: (G-Y) = –0.51
Adds a brightness signal: Y to each of (R-Y)’, (B-Y)’ and G-Y to create R, G, and B signals.
A composite video signal or brightness signal is input to the synchronizing separate input pin (pin 39) at 1 V
Separates the sync. signal from a composite video signal. The slice level can be changed using an external resistor:
R
The operation of the PC1830 sync. separation circuit is explained below.
Figure 5-6 is an equivalent circuit diagram of the PC1830 sync. separation circuit.
X
(see Figure 5-6, TYP. = 220 ).
Figure 5-6.
O
and R
V
X
CC
A733
by current I
1.8 k
Co
+
PC1830 Sync. Separate Input Section Equivalent Circuit
Ix
Rx
(when V
Approx. 2.5 V
X
Isp
during this cut-off period. Figure 5-7 illustrates this situation.
Ro
CC
= 5 V)
(R-Y)’ – 0.19
39
5 k
167
5 k
(B-Y)’
V
CC
SP
flows from the PC1830 to C
V
CC
100
TR1
16 k
5 k
O
so that the
P-P
PC1830
.
O