SC16C754 Philips Semiconductors, SC16C754 Datasheet - Page 6

• Manufacturer Part Number: SC16C754
• Description: Quad UART with 64-byte FIFO
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 2:
9397 750 11618
Product data
Symbol
CLKSEL
CSA, CSB,
CSC, CSD
CTSA, CTSB,
CTSC, CTSD
D0-D2,
D3-D7
DSRA, DSRB,
DSRC, DSRD
DTRA, DTRB,
DTRC, DTRD
GND
INTA, INTB,
INTC, INTD
INTSEL
IOR
Pin description
Pin
LQFP80 PLCC68
26
9, 13,
49, 53
4, 18,
44, 58
68-70,
71-75
3, 19,
43, 59
5, 17,
45, 57
16, 36,
56, 76
8, 14,
48, 54
67
51
…continued
30
16, 20,
50, 54
11, 25,
45, 59
66-68,
1-5
10, 26,
44, 60
12, 24,
46, 58
6, 23,
40, 57
15, 21,
49, 55
65
52
Type
I
I
I
I/O
I
O
I
O
I
I
Description
Clock Select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable
clock. During the reset, a logic 1 (V
prescaler. A logic 0 (GND) on CLKSEL selects the divide-by-4 prescaler.
The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1(V
CLKSEL will latch a 1 into MCR[7]. MCR[7] can be changed after RESET to
alter the prescaler value.
Chip Select (Active-LOW). These pins enable data transfers between the
user CPU and the SC16C754 for the channel(s) addressed. Individual
UART sections (A, B, C, D) are addressed by providing a logic LOW on the
respective CSA through CSD pins.
Clear to Send (Active-LOW). These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on the CTS pins indicates the
modem or data set is ready to accept transmit data from the SC16C754.
Status can be tested by reading MSR[4]. These pins only affect the transmit
and receive operations when Auto-CTS function is enabled via the
Enhanced Feature Register EFR[7] for hardware flow control operation.
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data stream.
Data Set Ready (Active-LOW). These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on these pins indicates the
modem or data set is powered-on and is ready for data exchange with the
UART. The state of these inputs is reflected in the modem status register
(MSR).
Data Terminal Ready (Active-LOW). These outputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates that the SC16C754 is powered-on and ready. These pins can be
controlled via the modem control register. Writing a logic 1 to MCR[0] will
set the DTR output to logic 0 (LOW), enabling the modem. The output of
these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
Signal and power ground.
Interrupt A, B, C, and D (Active-HIGH). These pins provide individual
channel interrupts INTA through INTD. INTA through INTD are enabled
when MCR[3] is set to a logic 1, interrupt sources are enabled in the
interrupt enable register (IER). Interrupt conditions include: receiver errors,
available receiver buffer data, available transmit buffer space, or when a
modem status flag is detected. INTA-INTD are in the high-impedance state
after reset.
Interrupt select (Active-HIGH with internal pull-down). INTSEL can be
used in conjunction with MCR[3] to enable or disable the 3-STate interrupts
INTA-INTD or override MCR[3] and force continuous interrupts. Interrupt
outputs are enabled continuously by making this pin a logic 1. Driving this
pin LOW allows MCR[3] to control the 3-State interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-State outputs.
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on
IOR will load the contents of an internal register defined by address bits
A0-A2 onto the SC16C754 data bus (D0-D7) for access by external CPU.
Rev. 04 — 19 June 2003
CC
) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on
CC
) on CLKSEL selects the divide-by-1
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
6 of 49