SC16C754 Philips Semiconductors, SC16C754 Datasheet - Page 31

• Manufacturer Part Number: SC16C754
• Description: Quad UART with 64-byte FIFO
• Manufacturer: Philips Semiconductors

Philips Semiconductors
9397 750 11618
Product data
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs
of both channels.
Table 22:
The FIFO Rdy register is a read-only register that can be accessed when any of the
two UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and
loop-back is disabled. The address is 111.
Bit
7-4
3-0
Symbol
FIFO Rdy[7:4]
FIFO Rdy[3:0]
FIFO Ready Register bits description
Rev. 04 — 19 June 2003
Description
0 = There are less than a RX trigger level number of characters
in the RX FIFO.
1 = The RX FIFO has more than a RX trigger level number of
characters available for reading or a time-out condition has
occurred.
0 = There are less than a TX trigger level number of spaces
available in the TX FIFO.
1 = There are at least a TX trigger level number of spaces
available in the TX FIFO.
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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