SC16C750B Philips Semiconductors, SC16C750B Datasheet - Page 27

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SC16C750B

Manufacturer Part Number
SC16C750B
Description
5 V/ 3.3 V and 2.5 V UART with 64-byte FIFOs
Manufacturer
Philips Semiconductors
Datasheet

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Product data
7.10 SC16C750B external reset conditions
7.9 Scratchpad Register (SPR)
Table 21:
[1]
The SC16C750B provides a temporary data register to store 8 bits of user
information.
Table 22:
Table 23:
Bit
1
0
Register
IER
ISR
LCR
MCR
LSR
MSR
FCR
EFR
Output
TX
RTS
DTR
RXRDY
TXRDY
INT
Whenever any MSR[0:3] is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[1]
MSR[0]
Modem Status Register bits description
Reset state for registers
Reset state for outputs
Rev. 03 — 13 December 2004
Reset state
IER[7:0] = 0
ISR[7:1] = 0; ISR[0] = 1
LCR[7:0] = 0
MCR[7:0] = 0
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR[7:4] = input signals; MSR[3:0] = 0
FCR[7:0] = 0
EFR[7:0] = 0
Description
DSR
CTS
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C750B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C750B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
[1]
[1]
Reset state
HIGH
HIGH
HIGH
HIGH (STD mode)
LOW (STD mode)
LOW (STD mode)
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
…continued
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C750B
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