SC16C652BIBS PHILIPS [NXP Semiconductors], SC16C652BIBS Datasheet - Page 11

• Manufacturer Part Number: SC16C652BIBS
• Description: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14452
Product data
6.6 Special feature software flow control
6.7 Hardware/software and time-out interrupts
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C652B automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C652B sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C652B will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0:3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0:3] to a logic 0.
The SC16C652B compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0:1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0:1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
The interrupts are enabled by IER[0:3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C652B will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The ISR register provides the current singular
highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may
mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending
interrupt will the lower priority CTS/RTS interrupt(s) be reflected in the status register.
Servicing the interrupt without investigating further interrupt conditions can result in
data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C652B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1 ,
1.5 , or 2 bit times.
9) shows each X-Register with eight bits of character information, the actual
Rev. 03 — 10 December 2004
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C652B
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