LTC2421 LINER [Linear Technology], LTC2421 Datasheet - Page 14

• Manufacturer Part Number: LTC2421
• Description: 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2421/LTC2422
external serial clock. If the change occurs during the con-
version state, the result of the conversion in progress may
be outside specifications but the following conversions
will not be affected. If the change occurs during the data
output state and the converter is in the Internal SCK mode,
the serial clock duty cycle may be affected but the serial
data stream will remain valid.
Table 3 summarizes the duration of each state as a func-
tion of F
SERIAL INTERFACE
The LTC2421/LTC2422 transmit the conversion results
and receives the start of conversion command through a
Table 3. LTC2421/LTC2422 State Duration
State
CONVERT
SLEEP
DATA OUTPUT
14
Figure 5. LTC2421/LTC2422 Normal Mode Rejection When
Using an External Oscillator of Frequency f
O
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–100
–110
–120
–130
–140
.
–60
–70
–80
–90
–12
Operating Mode
Internal Oscillator
External Oscillator
Internal Serial Clock
External Serial Clock with
Frequency f
–8
U
–4
U
SCK
0
kHz
4
W
8
24212 F05
EOSC
F
(60Hz Rejection)
F
(50Hz Rejection)
F
with Frequency f
(f
F
(Internal Oscillator)
F
Frequency f
12
O
O
O
O
O
EOSC
= LOW
= HIGH
= External Oscillator
= LOW/HIGH
= External Oscillator with
U
/2560 Rejection)
EOSC
EOSC
kHz
kHz
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the con-
verter status and during the data output state, it is used to
read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2421/LTC2422 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or
floating at power-up or during this transition, the con-
verter enters the internal SCK mode. If SCK is LOW at
power-up or during this transition, the converter enters
the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), drives the serial
data during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the con-
version and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
Duration
133ms
160ms
20510/f
As Long As CS = HIGH Until CS = 0 and SCK
As Long As CS = LOW But Not Longer Than 1.28ms
(24 SCK cycles)
As Long As CS = LOW But Not Longer Than 192/f
(24 SCK cycles)
As Long As CS = LOW But Not Longer Than 24/f
(24 SCK cycles)
EOSC
s
SCK
EOSC
ms
ms
24212f