LTC2421 LINER [Linear Technology], LTC2421 Datasheet - Page 12

• Manufacturer Part Number: LTC2421
• Description: 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2421/LTC2422
fault current, a resistor of up to 5k may be added in series
with the V
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
fore, the resistor should be located as close as practical to
the V
verter accuracy can be evaluated from the curves pre-
sented in the Analog Input/Reference Current section. In
addition, a series resistor will introduce a temperature de-
pendent offset error due to the input leakage current. A
1nA input leakage current will develop a 1ppm offset error
on a 5k resistor if V
temperature dependency.
Output Data Format
The LTC2421/LTC2422 serial output data stream is 24 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 20 bits are the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) for the LTC2422, this bit is LOW
if the last conversion was performed on CH0 and HIGH for
CH1. This bit is always LOW for the LTC2421.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (fourth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
12
IN
pin. The effect of the series resistance on the con-
IN
pin without affecting the performance of the
IN
SDO
SCK
CS
is >0, this bit is HIGH. If V
U
REF
Hi-Z
SLEEP
= 5V. This error has a very strong
U
IN
BIT 23
pin as low as possible; there-
EOC
1
CH0/CH1
W
BIT 22
2
BIT 21
IN
SIG
Figure 4. Output Data Timing
U
is <0, this
3
BIT 20
EXT
4
DATA OUTPUT
BIT 19
MSB
0 V
normal input range, V
The function of these bits is summarized in Table 1.
Table 1. LTC2421/LTC2422 Status Bits
Input Range
V
0 < V
V
V
*Bit 22 displays the channel number for the LTC2422. Bit 22 is always
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This sig-
nal may be used as an interrupt for an external microcon-
troller. Bit 23 (EOC) can be captured on the first rising edge
of SCK. Bit 22 is shifted out of the device on the first falling
edge of SCK. The final data bit (Bit 0) is shifted out on the
falling edge of the 23rd SCK and may be latched on the
rising edge of the 24th SCK pulse. On the falling edge of the
24th SCK pulse, SDO goes HIGH indicating a new conver-
sion cycle has been initiated. This bit serves as EOC (Bit
23) for the next conversion cycle. Table 2 summarizes the
output data format.
0 for the LTC2421
IN
IN
IN
5
> V
= 0
< 0
IN
+
IN
REF
/0
V
–
REF
V
19
REF
, this bit is LOW. If the input is outside the
BIT 4
Bit 23
20
EOC
0
0
0
0
IN
LSB
> V
BIT 0
20
24
REF
CH0/CH1
Bit 22
*0/1
*0/1
*0/1
*0/1
or V
CONVERSION
IN
< 0, this bit is HIGH.
24212 F04
Bit 21
SIG
1/0
1
1
0
Bit 20
EXR
1
0
0
1
24212f