LTC2272CUJ LINER [Linear Technology], LTC2272CUJ Datasheet - Page 6

• Manufacturer Part Number: LTC2272CUJ
• Description: 16-Bit, 80Msps/65Msps Serial Output ADC
• Manufacturer: LINER [Linear Technology]

LTC2273/LTC2272
range, otherwise specifi cations are at T
TIMING CHARACTERISTICS
POWER REQUIREMENTS
SYMBOL PARAMETER
V
P
OV
I
I
P
range, otherwise specifi cations are at T
SYMBOL PARAMETER
f
t
t
t
t
t
t
t
t
t
t
LAT
LAT
LAT
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
Note 4: V
wave with 1.6V common mode, input range = 2.25V
drive (PGA = 0), unless otherwise specifi ed.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from
a “best fi t straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
6
VDD
OVDD
S
CONV
L
H
AP
BIT
JIT
R
SU
HD
CS
DD
SHDN
DIS
, t
DD
, UI
P
SC
SD
F
DD
Analog Supply Voltage
Shutdown Power
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power Dissipation
Sampling Frequency
Conversion Period
ENC Clock Low Time
ENC Clock High Time
Sample-and-Hold Aperture Delay
Period of a Serial Bit
Total Jitter of CMLOUT± (P-P)
Differential Rise and Fall Time of
CMLOUT± (20% to 80%)
SYNC to ENC Clock Setup Time
ENC Clock to SYNC Hold Time
ENC Clock to SYNC Delay
Pipeline Latency
Latency from SYNC Active to COMMA Out
Latency from SYNC Release to DATA Out
= 3.3V, f
SAMPLE
= 105MHz differential ENC
CONDITIONS
SHDN = V
CMLOUT Directly-Coupled, 50Ω to OV
CMLOUT Directly-Coupled, 100Ω Diff. (Note 7)
CMLOUT AC-Coupled (Note 7)
DC Input
CMLOUT Directly-Coupled, 50Ω to OV
CMLOUT Directly-Coupled, 100Ω Diff.
CMLOUT AC-Coupled
DC Input
A
A
DD
= 25°C. A
= 25°C. (Note 4)
without latchup.
DD
P-P
+
CONDITIONS
(Note 9)
(Note 7)
(Note 7)
BER = 1E–12 (Note 7)
R
(Note 7)
(Note 7)
(Note 7)
(Note 7)
/ENC
with differential
The
TERM
IN
The
–
l
= –1dBFS. (Note 4)
= 50Ω, C
= 2V
denotes the specifi cations which apply over the full operating temperature
l
DD
denotes the specifi cations which apply over the full operating temperature
P-P
, they
sine
L
= 2pF
DD
DD
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
input range = 2.25V
Note 9: Recommended operating conditions.
Note 10: The dynamic current of the switched capacitors analog inputs
can be large compared to the leakage current and will vary with the sample
rate.
Note 11: Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1k.
l
l
l
l
l
l
l
l
(Note 7)
4.06
4.06
MIN
2.5
t
20
50
HD
2
DD
= 3.3V, f
l
l
l
l
l
t
LTC2273
CONV
6.25
6.25
TYP
1/f
110
0.7
3.135
9
3
2
MIN
1.2
1.4
1.4
P-P
S
/20
SAMPLE
with differential drive.
t
LTC2273
CONV
1100
TYP
233
3.3
MAX
0.35
16
16
= 80Msps (LTC2273) or 65Msps (LTC2272)
5
8
80
25
25
– t
SU
3.465 3.135
1221
MAX
V
V
V
370
DD
DD
DD
5.03
5.03
MIN
2.5
t
20
50
HD
2
MIN
1.2
1.4
1.4
t
LTC2272
CONV
7.69
7.69
TYP
1/f
110
0.7
LTC2272
9
3
2
S
TYP
300
990
/20
3.3
16
16
5
8
t
CONV
MAX
3.465
0.35
1122
MAX
V
V
V
340
65
25
25
DD
DD
DD
– t
SU
UNITS
Cycles
Cycles
Cycles
UNITS
22732f
MHz
mW
mW
mA
mA
mA
mA
ns
ns
ns
UI
ps
ns
ns
ns
V
V
V
V
s
s