LTC2272CUJ LINER [Linear Technology], LTC2272CUJ Datasheet - Page 26

• Manufacturer Part Number: LTC2272CUJ
• Description: 16-Bit, 80Msps/65Msps Serial Output ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2273/LTC2272
Driving the Encode Inputs
The noise performance of the LTC2273/LTC2272 can
depend on the encode signal quality as much as for the
analog input. The encode inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC oper-
ating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
3. If the ADC is clocked with a fi xed frequency sinusoidal
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.4V
to 3V. Each input may be driven from ground to V
single-ended drive.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2273 is
80Msps. The maximum conversion rate for the LTC2272
is 65Msps.
The lower limit of the LTC2273/LTC2272 sample rate is
determined by the PLL minimum operating frequency of
20Msps.
26
former coupling, use a higher turns ratio to increase the
amplitude.
signal, fi lter the encode signal to reduce wideband
noise.
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
DD
for
For the ADC to operate properly, the internal CLK signal
should have a 50% duty cycle. A duty cycle stabilizer cir-
cuit has been implemented on chip to facilitate non-50%
ENC duty cycles.
Data Format
The MSBINV pin selects the ADC data format. A low level
selects offset binary format (code 0 corresponds to –FS, and
code 65535 corresponds to +FS). A high level on MSBINV
selects 2’s complement format (code –32768 corresponds
to –FS and code 32767 corresponds to +FS.
Shutdown Modes
The assertion of both SHDN pins will shut down the ADC
and the serial interface and place the chip in a low-cur-
rent mode.
Internal Dither
The LTC2273/LTC2272 are 16-bit ADC with a very linear
transfer function; however, at low input levels even slight
imperfections in the transfer function will result in unwanted
tones. Small errors in the transfer function are usually a
result of ADC element mismatches. An optional internal
dither mode can be enabled to randomize the input location
on the ADC transfer curve, resulting in improved SFDR
for low signal levels.
As shown in Figure 11, the output of the sample-and-hold
amplifi er is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted digitally from the ADC result. If the
dither DAC is precisely calibrated to the ADC, very little
of the dither signal will be seen at the output. The dither
signal that does leak through will appear as white noise.
The dither DAC is calibrated to result in less than 0.5dB
elevation in the noise fl oor of the ADC, as compared to
the noise fl oor with dither off.
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