LTC2272CUJ LINER [Linear Technology], LTC2272CUJ Datasheet - Page 15

• Manufacturer Part Number: LTC2272CUJ
• Description: 16-Bit, 80Msps/65Msps Serial Output ADC
• Manufacturer: LINER [Linear Technology]

V
GND with 0.1μF ceramic chip capacitors.
GND (Pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40,
41): ADC Power Ground.
A
A
ENC
sampled analog input is held on the rising edge of ENC
This pin is internally biased to 1.6V through a 6.2k resistor.
Output data can be latched on the falling edge of ENC
ENC
sampled analog input is held on the falling edge of ENC-.
This pin is internally biased to 1.6V through a 6.2kΩ
resistor. Bypass to ground with a 0.1uF capacitor for a
single-ended Encode signal.
DITH (Pin 15): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of this data sheet for details
on dither operation.
ISMODE (Pin 16): Idle Synchronization mode. When IS-
MODE is not asserted, synchronization is performed with
a series of COMMAS (K28.5). When ISMODE is asserted,
a special Idle SYNC mode is enabled where synchroniza-
tion is performed by sending a COMMA (K28.5) followed
by the appropriate data code-group (D5.6 or D16.2) for
establishing a negative running disparity for the fi rst data
code-group after synchronization.
PIN FUNCTIONS
DD
IN
IN
+
–
+
–
(Pins 1, 2, 12, 13 ): Analog 3.3V Supply. Bypass to
(Pin 4): Positive Differential Analog Input.
(Pin 5): Negative Differential Analog Input.
(Pin 10): Negative Differential Encode Input. The
(Pin 9): Positive Differential Encode Input. The
+
.
+
.
SRR0 (Pin 17): Sample Rate Range Select Bit0. Used with
the SRR1 pin to select the sample rate operating range.
SRR1 (Pin 18): Sample Rate Range Select Bit1. Used with
the SRR0 pin to select the sample rate operating range.
SHDN (Pins 19, 20): Shutdown Pins. A high level on both
pins will shut down the chip. A low level is required for
normal operation.
OV
ers. Typically 1.2V to 3.3V. The minimum supply is 1.4V
when applying a differential termination on the CMLOUT
pins or when AC-coupling the CMLOUT pins. Bypass to
ground with 0.1μF ceramic chip capacitor.
CMLOUT
CMLOUT
SYNC
Low for Compatibility with JESD204). A low level on this
pin for at least two sample clock cycles will initiate frame
synchronization.
SYNC
level on this pin for at least two sample clock cycles will
initiate frame synchronization. For single-ended operation,
bypass to ground with a 0.1μF capacitor and use SYNC
as the SYNC point.
DD
+
–
(Pins 22, 25): Positive Supply for the Output Driv-
(Pin 29): Sync Request Negative Input. A high
(Pin 28): Sync Request Positive Input (Active
–
+
(Pin 23): Negative High-Speed CML Output.
(Pin 24): Positive High-Speed CML Output.
LTC2273/LTC2272
15
22732f
+