C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 23
C505_9708
Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C505_9708.pdf
(227 pages)
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3.1
The C505-2R has 16 Kbytes of read-only program memory which can be externally expanded up
to 64 Kbytes. If the EA pin is held high, the C505-2R executes program code out of the internal ROM
unless the program counter address exceeds 3FFF H . Address locations 4000 H through FFFF H are
then fetched from the external program memory. If the EA pin is held low, the C505 fetches all
instructions from the external program memory.
3.2
The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks : the lower 128
bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose
registers, occupy locations 0 through 1F H in the lower RAM area. The next 16 bytes, locations 20 H
through 2F H , contain 128 directly addressable bit locations. The stack can be located anywhere in
the internal RAM area, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions
that use a 16-bit or an 8-bit address. The internal CAN controller (C505C only) and the internal
XRAM are located in the external memory address area at addresses F700 H to F7FF H and FF00 H
to FFFF H respectively. The CAN controller registers and internal XRAM can therefore be accessed
using MOVX instructions with addresses pointing to the respective address areas.
3.3
The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the
PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or
interrupt service routines.
The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).
Reset initializes the stack pointer to location 07 H and increments it once to start from location 08 H
which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.
Semiconductor Group
Program Memory, "Code Space"
Data Memory, "Data Space"
General Purpose Registers
3-2
Memory Organization
C505 / C505C
1997-08-01
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