C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet
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C505_9708
Related parts for C505_9708
C505_9708 Summary of contents
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C505 C505 C 8-Bit CMOS Microcontroller User's Manual 08.97 ...
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C505 User’s Manual Revision History : Previous Releases : Page Page Subjects (changes since last revision) (previous (new version) version) Edition 1997-08-01 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6.4.2 CAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 10 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The C505 microcontroller is a member of the Siemens C500 family of 8-bit microcontrollers. The C505 is fully compatible to the standard 8051 microcontroller. Additionally the C505 provides extended power save provisions, on-chip RAM, 16K of on-chip program ...
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Listed below is a summary of the main features of the C505 family: • Fully compatible to standard 8051 microcontroller • Superset of the 8051 architecture with 8 datapointers • MHz operating frequency – 375 ns instruction ...
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V AREF V AGND XTAL1 XTAL2 RESET EA ALE PSEN RXDC TXDC C505C only Figure 1-2 Logic Symbol Semiconductor Group Port 8-Bit Digital Port 8-Bit Digital 8-Bit Analog Inputs ...
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Pin Configuration This section shows the pin configuration of the C505 in the P-MQFP-44 package. P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V AGND P1.0 / AN0 / INT3 / CCO P1.1 ...
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Pin Definitions and Functions This section describes all external signals of the C505 with its function. Table 1-1 Pin Definitions and Functions Symbol Pin Number P1.0-P1.7 40-44,1 Input ...
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Table 1-1 Pin Definitions and Functions Symbol Pin Number RESET 4 P3.0-P3 Input O = Output Semiconductor Group I/O*) Function I RESET A high level on this ...
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Table 1-1 Pin Definitions and Functions Symbol Pin Number P4.0 6 P4.1 28 XTAL2 14 XTAL1 Input O = Output Semiconductor Group I/O*) Function I/O Port 4 I 2-bit quasi-bidirectional port with internal pull-up ...
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Table 1-1 Pin Definitions and Functions Symbol Pin Number P2.0-P2.7 18-25 PSEN 26 ALE Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit quasi-bidirectional I/O port with internal pullup resistors. ...
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Table 1-1 Pin Definitions and Functions Symbol Pin Number EA 29 P0.0-P0.7 37- AREF 39 V AGND Input O = Output Semiconductor Group I/O*) Function I External Access Enable ...
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Fundamental Structure The C505 is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C505 incorporates a CPU with 8 datapointers, an 8-bit A/D converter, a ...
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V C505 CC V Oscillator SS Watchdog XTAL1 OSC & Timing XTAL2 CPU RESET 8 Datapointers ALE Programmable PSEN Watchdog Timer EA Timer 0 Timer 1 Timer 2 USART Baudrate Generator Full-CAN Controller Interrupt Unit Converter ...
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CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set ...
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Special Function Register PSW (Address Bit No. MSB Bit Function CY Carry Flag Used by arithmetic instructions. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 ...
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CPU Timing The C505 has no clock prescaler. Therefore, a machine cycle of the C505 consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine ...
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OSC (XTAL2) ALE Read Opcode S1 S2 (a) 1-Byte, 1-Cycle Instruction INC A Read Opcode S1 S2 (b) 2-Byte, 1-Cycle Instruction ADD A #DATA Read Opcode S1 S2 (c) 1-Byte, ...
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Memory Organization The C505 CPU manipulates operands in the following four address spaces: – Kbytes of program memory (16K on-chip program memory for C505-2R) – Kbytes of external data memory – 256 bytes ...
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Program Memory, "Code Space" The C505-2R has 16 Kbytes of read-only program memory which can be externally expanded Kbytes. If the EA pin is held high, the C505-2R executes program code out of the internal ROM ...
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XRAM Operation The XRAM in the C505 is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same ...
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After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM and CAN controller are generally disabled. In this case, all accesses using MOVX instructions within the address range of F700 H to FFFF H generate ...
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Accesses to XRAM using the DPTR (16-bit Addressing Mode) The XRAM and CAN controller can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are : – MOVX A, @DPTR – MOVX ...
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Write to Port 2 Figure 3-2 Write Page Address to Port 2 “MOV P2,pageaddress“ will write the page address to port 2 and the XPAGE-Register. When external RAM accessed in the XRAM/CAN controller address range, the XRAM/CAN ...
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Write to XPAGE Figure 3-3 Write Page Address to XPAGE “MOV XPAGE,pageaddress“ will write the page address only to the XPAGE register. Port 2 is available for addresses or I/O data. Semiconductor Group Port 0 CAN-Controller XPAGE Port 2 3-7 ...
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Write I/O Data to Port 2 Figure 3-4 Use of Port 2 as I/O Port At a write to port 2, the XRAM/CAN controller address in XPAGE register will be overwritten because of the concurrent write to port 2 and ...
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The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM/CAN Controller address range, an external access is performed. For the C505 the ...
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MOVX DPTR a)P0/P2 Bus @DPTR < b)RD/WR active XRAM/CAN c)ext.memory is address used range DPTR a)P0/P2 Bus (RD/WR-Data) XRAM/CAN b)RD/WR address inactive range c)XRAM/CAN is used MOVX XPAGE a)P0 Bus @ Ri < P2 I/O XRAM/CAN b)RD/WR active addr.page ...
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Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area ...
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Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer SYSCON ...
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Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Serial ADCON0 2) A/D Converter Control Register 0 2) Channel PCON Power Control Register SBUF Serial Channel Buffer Register SCON Serial Channel Control Register SRELL Serial Channel Reload ...
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Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name CAN CR Control Register Controller SR Status Register (C505C) IR Interrupt Register BTR0 Bit Timing Register Low BTR1 Bit Timing Register High GMS0 Global Mask Short Register Low ...
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Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after 1) Reset DPL DPH 00 H ...
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Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after 1) Reset SYSCON XX10- 0X01 IEN1 ...
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Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after 1) Reset DC H ADCON1 01XX- X000 ACC XXXX- XX11 B 2) ...
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Table 3-4 Contents of the CAN Registers in numeric order of their addresses (C505C only) Addr. Register Content n=1-F H after 2) 1) Reset F700 F701 F702 F704 ...
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Table 3-4 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505C only) Addr. Register Content n=1-F H after 2) 1) Reset F7n7 H DB0n XX H F7n8 H DB1n XX H F7n9 H DB2n XX H ...
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External Bus Interface The C505 allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C505 is used in ...
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One Machine Cycle S1 S2 ALE PSEN RD PCH P2 OUT INST PCL P0 IN OUT PCL OUT valid b) One Machine Cycle S1 S2 ALE PSEN RD PCH P2 OUT INST PCL P0 IN OUT PCL OUT valid ...
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Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in ...
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ALE, Address Latch Enable The C505 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 and PC 3FFF H ) and ALE is switched off by EALE=0, then, ALE will only go active ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation ...
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Eight Datapointers for Faster External Bus Access 4.6.1 The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to ...
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DPSEL( DPSEL Selected Data- pointer . DPTR DPTR DPTR DPTR ...
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Example 1 : Using only One Datapointer (Code for a C501) Initialization Routine MOV LOW(SRC_PTR), #0FFH MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H MOV HIGH(DES_PTR), #2FH Table Look-up Routine under Real Time Conditions PUSH DPL PUSH DPH MOV DPL, LOW(SRC_PTR) MOV ...
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Example 2 : Using Two Datapointers (Code for a C505) Initialization Routine MOV DPSEL, #06H MOV DPTR, #1FFFH MOV DPSEL, #07H MOV DPTR, #2FA0H Table Look-up Routine under Real Time Conditions PUSH DPSEL MOV DPSEL, #06H ;INC DPTR ;CJNE … ...
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ROM Protection for the C505 The C505-2R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a ...
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Protected ROM Mode If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in ...
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After each 16th data byte the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail and high for ...
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Version Registers Version registers are typically used for adapting the programming firmware to specific device characteristics such as ROM / OTP size etc. Three version registers are implemented in the C505. They can be read during normal program execution ...
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System Reset 5.1 Hardware Reset Operation The hardware reset function incorporated in the C505 allows for an easy automatic start- minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function ...
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The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least for a crystal oscillator. This requirement is typically met using a capacitor ...
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Fast Internal Reset after Power-On The C505 uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family ...
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Figure 5-2 Power-On Reset of the C505 Semiconductor Group 5-4 System Reset C505 / C505C 1997-08-01 ...
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Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to ...
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Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The ...
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Crystal or ceramic resonator Figure 5-5 On-Chip Oscillator Circuiry To drive the C505 with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-6. XTAL2 has to be left unconnected. ...
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System Clock Output For peripheral devices requiring a system clock, the C505 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special ...
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ALE PSEN RD,WR CLKOUT Figure 5-7 Timing Diagram - System Clock Output Semiconductor Group 5-9 System Reset C505 / C505C MCT01858 1997-08-01 ...
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On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the C505 except for the integrated interrupt controller, which is described separately in chapter 7. 6.1 Parallel I/O The C505 has four 8-bit I/O ports and ...
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As already mentioned, port 1, 3 and 4 are provided for multiple alternate functions. These functions are listed in table 6-2: Table 6-2 Alternate Functions of Port 1, 3 and 4 Port Second / third Port Function Type P1.0 AN0 ...
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Standard I/O Port Circuitry Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented ...
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The output drivers of Port have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output used as an input, the port bit stored in the bit ...
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Port 0 Circuitry Port 0, in contrast to ports considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET ...
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Port 1, Port 3 and Port 4 Circuitry The pins of ports 1, 3 and 4 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-2. Figure 6-4 shows a functional ...
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Port 2 Circuitry As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this ...
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Addr. Q MUX Delay 1 State = 1 Input Data (Read Pin) Figure 6-5a Port 2 Pull-up Arrangement Port 2 in I/O function works similar to the Type B port driver circuitry (section 6.1.3.1) whereas in address output function it ...
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Detailed Output Driver Circuitry In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup arrangements. The differences of the port types available in the C505 are described in the next sections. 6.1.3.1 Type ...
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The pullup FET p-channel type only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall ...
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Type C Port Driver Circuitry Figure 6-7 shows the port driver circuit of the type C mixed digital/analog I/O port 1 lines of the C505. The analog function is selected by the bits in the SFR P1ANA. When analog ...
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Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output ...
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Port Loading and Interfacing The output buffers of ports can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the ...
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Read-Modify-Write Feature of Ports Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the ...
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Timers/Counters The C505 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it ...
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Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers ...
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Special Function Register TCON (Address Bit No. MSB TF1 TR1 The shaded bits are not used for controlling timer/counter 0 and 1. Bit Function TR0 Timer 0 run control ...
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Special Function Register TMOD (Address Bit No. MSB Gate C/T Timer 1 Control Bit Function GATE Gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" ...
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Mode 0 Putting either timer/counter 0,1 into mode 0 configures 8-bit timer/counter with a divide-by- 32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. ...
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Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-10. OSC ÷ 6 P3.4/ Gate P3.2/INT0 Figure 6-10 Timer/Counter ...
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Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-11. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is ...
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Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 ...
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Timer/Counter 2 with Additional Compare/Capture/Reload The timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C505. lt can be used for all kinds of digital signal generation and event capturing like pulse ...
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P1.5/ Sync. T2EX P1.7/ Sync. T2 ÷6 f OSC OSC ÷12 T2PS 16 Bit Comparator Comparator CCL3/CCH3 CCL2/CCH2 Figure 6-13 Timer 2 Block Diagram Semiconductor Group On-Chip Peripheral Components T2I0 T2I1 EXEN2 & Reload 16 Bit 16 Bit Comparator CCL1/CCH1 ...
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Timer 2 Registers This chapter describes all timer 2 related special function registers of timer 2. The interrupt related SFRs are also included in this section. Table 6-5 summarizes all timer 2 SFRs. Table 6-5 Special Function Registers of ...
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The T2CON timer 2 control register is a bit-addressable register which controls the timer 2 function and the compare mode of registers CRC, CC1 to CC3. Special Function Register T2CON (Address Bit No. MSB ...
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Special Function Register TL2 (Address Special Function Register TH2 (Address Special Function Register CRCL (Address Special Function Register CRCH (Address Bit No. MSB ...
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Special Function Register IEN0 (Address Special Function Register IEN1 (Address Special Function Register IRCON (Address MSB Bit No EAL WDT Bit No ...
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Special Function Register CCEN (Address Bit No. MSB COCAH3 COCAL3 COCAH2 COCAL2 Bit Function COCAH3 Compare/capture mode for CC register 3 COCAL3 COCAH3 COCAH2 Compare/capture mode for CC register ...
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Timer 2 Operation The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. The detailed operation is described below. Timer Mode In timer function, the count rate is derived from the oscillator ...
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Reload of Timer 2 The reload mode for timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON. Figure 6-14 shows the configuration of timer 2 in reload mode. Mode 0 : When timer 2 rolls over from ...
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Compare Function of Registers CRC, CC1 to CC3 The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. lf the ...
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Compare Register Circuit Compare Reg. 16 Bit Comparator Compare 16 Bit Match Timer Register Timer Timer Circuit Overflow Figure 6-15 Port Latch in Compare Mode 0 Compare Register CCx 16-Bit Comparator 16-Bit TH2 TL2 Timer 2 Figure 6-16 Timer 2 ...
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Contents ~ ~ of Timer 2 Timer Count = Reload Value Interrupt can be generated on overflow Compare Output (P1.x/CCx) Figure 6-17 Function of Compare Mode 0 6.2.2.3.2 Modulation Range in Compare Mode 0 Generally it can be said that ...
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CCHx/CCLx = 0000 or = CRCH/CRCL (maximum duty cycle) P1.x b) CCHx/CCLx = FFFF (minimum duty cycle) P1.x Figure 6-18 Modulation Range of a PWM Signal, generated with a Timer 2/CCx Register Combination in Compare Mode 0* The following ...
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Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output signal commonly used when output signals are not related to a constant signal period ( standard PWM Generation) but ...
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Compare Register Circuit Compare Reg. 16 Bit Comparator Compare 16 Bit Match Timer Register Timer Circuit Figure 6-19 Port Latch in Compare Mode 1 Compare Register CCx 16 Bit Comparator 16 Bit TH2 TL2 Timer 2 Figure 6-20 Timer 2 ...
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Using Interrupts in Combination with the Compare Function The compare service of registers CRC, CC1, CC2 and CC3 are assigned to alternate output functions at port pins P1.0 to P1.3. Another option of these pins is that they can ...
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The second configuration which should be noted is when compare function is combined with negative transition activated interrupts. lf the port latch of port P1.0 contains a 1, the interrupt request flags IEX3 will immediately be set after enabling the ...
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Capture Function Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. ...
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CRCL" P1.0/INT 3/ CC0 T2 CON.6 Figure 6-21 Timer 2 - Capture with Register CRC Semiconductor Group On-Chip Peripheral Components Input TL2 Clock Mode 1 Capture Mode 0 CRCL 6-41 C505 / C505C Timer 2 Interrupt TH2 TF2 ...
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CCL1" P1.1/INT 4/ CC1 Figure 6-21a Timer 2 - Capture with Registers CC1 to CC3 Semiconductor Group On-Chip Peripheral Components Input TL2 Clock Mode 1 Capture Mode 0 CCL1 6-42 C505 / C505C Timer 2 Interrupt TH2 TF2 ...
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Serial Interface The serial port of the C505 is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read ...
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Multiprocessor Communication Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that ...
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Special Function Register SCON (Address Special Function Register SBUF (Address Bit No. MSB SM0 SM1 Bit Function SM0 Serial port 0 operating mode selection ...
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Baud Rate Generation There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between "baud rate clock" and "baud ...
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Timer 1 Overflow Baud Rate Generator f OSC (SRELH SRELL) ÷ 6 Note: The switch configuration shows the reset state. Figure 6-22 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for ...
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Baud Rate in Mode 1 and 3 In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1. 6.3.3.3.1 Using the Internal Baud Rate Generator In modes 1 ...
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Special Function Register SRELH (Address Special Function Register SRELL (Address Bit No. MSB – – The shaded bits are not used for reload operation. Bit Function ...
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Using Timer 1 to Generate Baud Rates In mode 1 and 3 of the serial port also timer 1 can be used for generating baud rates. Then the baud rate is determined by the timer 1 overflow rate and ...
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Details about Mode 0 Serial data enters and exists through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at Figure 6-24 shows a simplified functional diagram of the ...
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Write to SBUF S D CLK Baud Rate S6 Clock & REN RI Figure 6-24 Serial Interface, Mode 0, Functional Diagram Semiconductor Group On-Chip Peripheral Components Internal Bus Q SBUF Zero Detector Start Shift TX Control Send TX Clock ...
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Figure 6-25 Serial Interface, Mode 0, Timing Diagram Semiconductor Group On-Chip Peripheral Components Transmit 6-53 C505 / C505C Receive 1997-08-01 ...
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Details about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The ...
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Write to SBUF S D CLK ÷ 16 Baud Rate Clock Sample 1-to-0 Transition Detector RXD Figure 6-26 Serial Interface, Mode 1, Functional Diagram Semiconductor Group On-Chip Peripheral Components Internal Bus 1 Q SBUF Zero Detector Shift Start TX Control ...
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Transmit Figure 6-27 Serial Interface, Mode 1, Timing Diagram Semiconductor Group On-Chip Peripheral Components Receive 6-56 C505 / C505C 1997-08-01 ...
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Details about Modes 2 and 3 Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th ...
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TB8 Write to SBUF S D CLK ÷ 16 Baud Rate Clock Sample 1-to-0 Transition Detector RXD Figure 6-28 Serial Interface, Mode 2 and 3, Functional Diagram Semiconductor Group On-Chip Peripheral Components Internal Bus Q SBUF Zero Detector Stop Bit ...
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Transmit Figure 6-29 Serial Interface, Mode 2 and 3, Timing Diagram Semiconductor Group On-Chip Peripheral Components Receive 6-59 C505 / C505C 1997-08-01 ...
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The On-Chip CAN Controller The Controller Area Network (CAN) bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency. Efficiency in this context means: – Transfer speed (data ...
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Basic CAN Controller Functions The on-chip CAN controller combines several functional blocks (see figure 6-30) that work in parallel and contribute to the controller’s performance. These units and the functions they provide are described below. The CAN controller provides ...
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Messages Handlers Status + Control to internal Bus Figure 6-30 CAN Controller Block Diagram Semiconductor Group On-Chip Peripheral Components TXDC BTL-Configuration CRC Gen./Check TX/RX Shift Register Messages Intelligent Memory Interrupt Register Bit Stream Processor Status Register 6-62 C505C Only RXDC ...
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TX/RX Shift Register The Transmit / Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of ...
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Intelligent Memory The Intelligent Memory (CAM/RAM array) provides storage for message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the ...
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CAN Register Description Notational Conventions Each CAN register is described with its bit symbols, address, reset value, and a functional description of each bit or bitfield. Also the access type is indicated for each bit or bitfield : r ...
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CAN Register Address Area F700 H General Registers F710 H Message Object 1 F720 H Message Object 2 F730 H Message Object 3 F740 H Message Object 4 F750 H Message Object 5 F760 H Message Object 6 F770 H ...
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CAN Control Register CR (Address F700 H ) Bit No. MSB 7 6 F700 H TEST CCE rw rw Bit Function TEST Test mode Make sure that bit 7 is cleared when writing to the control register, as this bit ...
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CAN Status Register SR (Address F701 H ) Bit No. MSB 7 6 F701 H BOFF EWRN r r Bit Function BOFF Busoff status Indicates when the CAN controller is in busoff state (see EML). EWRN Error warning status Indicates ...
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Bit Function LEC Last error code This field holds a code which indicates the type of the last error occurred on the CAN bus message has been transferred (reception or transmission) without error, this field will be cleared. ...
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CAN Interrupt Register IR (Address F702 H ) Bit No. MSB 7 6 F702 H Bit Function INTID Interrupt identifier This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”. See also ...
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CAN Bit Timing Register Low BTR0 (Address F704 H ) Bit No. MSB 7 6 F704 H SJW rw Bit Function SJW (Re)Synchronization jump width Adjust the bit time by (SJW+1) time quanta for resynchronization. BRP Baud rate prescaler For ...
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Mask Registers Messages can use standard or extended identifiers. Incoming frames are masked with their appropriate global masks. Bit IDE of the incoming message determines, if the standard 11-bit mask in global mask short used, or the ...
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CAN Upper Global Mask Long Register Low UGML0 (Addr. F708 H ) CAN Upper Global Mask Long Register High UGML1 (Addr. F709 H ) CAN Lower Global Mask Long Register Low LGML0 (Addr. F70A H ) CAN Lower Global Mask ...
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CAN Upper Mask of Last Message Register Low UMLM0 (Addr. F70C H ) Reset Value : UU H CAN Upper Mask of Last Message Register High UMLM1 (Addr. F70D H ) Reset Value : UU H CAN Lower Mask of ...
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The Message Object Registers / Data Bytes The message object is the primary means of communication between microcontroller and CAN controller. Each of the 15 message objects uses 15 consecutive bytes (see figure 6-32) and starts at an address ...
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Each element of the message control register is made of two complementary bits. This special mechanism allows to selectively set or reset specific elements (leaving others unchanged) without requiring read-modify-write cycles. None of these elements will be affected by reset. ...
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Bit Function RMTPND Remote pending (used for transmit-objects) Indicates that the transmission of this message object has been requested by a remote node, but the data has not yet been transmitted. When RMTPND is set, the CAN controller also sets ...
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Arbitration Registers The arbitration registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages. A received message is stored into the valid message object with a matching identifier and DIR=”0” (data frame) or ...
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CAN Upper Arbitration Register Low UAR0 (Address F7n2 H ) CAN Upper Arbitration Register High UAR1 (Address F7n3 H ) CAN Lower Arbitration Register Low LAR0 (Address F7n4 H ) CAN Lower Arbitration Register High LAR1 (Address F7n5 H ) ...
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Message Configuration and Data The following fields hold a description of the message within this object. The data field occupies the following 8 byte positions after the message configuration register. Note: There is no “don’t care” option for bits XTD ...
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CAN Data Bytes DB0-DB7 (Addresses F7n7 H -F7nE H ) Bit No. MSB F7n7 F7nE Message data for message object 15 (last message) will be written into a two-message-alternating buffer to ...
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No TXRQ = 1 CPUUPD = 0 Yes NEWDAT load message into buffer send message No transmission successful ? Yes NEWDAT = 1 Yes No TXIE =1 Yes INTPND Figure 6-33 CAN Controller Handling of Message ...
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No TXRQ = 1 CPUUPD = 0 Yes NEWDAT load identifier and control into buffer send remote frame No transmission successful ? Yes TXRQ RMTPND TXIE = 1 Yes INTPND Figure ...
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Power Up Initialization Update: Start Update Update: End TXRQ 0:reset 1:set Figure 6-35 Microcontroller Handling of Message Objects with Direction = transmit Semiconductor Group On-Chip Peripheral Components (all bits undefined) TXIE: = (application specific) RXIE: = (application specific) ...
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Power Up Initialization Process:Start Process Process:End 0:reset 1:set Figure 6-36 Microcontroller Handling of Message Objects with Direction = receive Semiconductor Group On-Chip Peripheral Components (all bits undefined) TXIE: = (application specific) RXIE: = (application specific) INTPND RMTPND: = ...
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Power Up Initialization Process:Start Process Process:End 0:reset 1:set Figure 6-37 Microcontroller Handling of the Last Message Object Semiconductor Group On-Chip Peripheral Components (all bits undefined) RXIE: = (application specific) INTPND RMTPND MSGLST Identifier: = ...
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MCU releases Buffer 2 MCU allocates Buffer 2 Buffer 1 = released Buffer 2 = allocated MCU access to Buffer 2 Store received Message into Buffer 1 Buffer 1 = allocated Buffer 2 = allocated MCU access to Buffer 2 ...
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Initialization and Reset The CAN controller is reset by a hardware reset, the oscillator watchdog reset watchdog timer reset of the C505C. A reset operation of the CAN controller performs the following actions : – sets ...
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Special Function Register SYSCON (Address Bit No. MSB 7 6 – – The functions of the shaded bits are not described here. Bit Function CMOD Prescaler selection for CAN controller Control bit for CAN controller ...
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The initialization of the message objects is independent of the state of bit INIT and can be done on the fly, the message objects should all be configured to particular identifiers or set to not valid before the BSP starts ...
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The bit time is determined by the C505C clock period CLP (see AC characteristics), the Baud Rate Prescaler, and the number of time quanta per bit: bit time = t Sync-Seg Sync-Seg TSEG1 + ...
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Hard Synchronization and Resynchronization To compensate phase shifts between clock oscillators of different CAN controllers, any CAN controller has to synchronize on any edge from recessive to dominant bus level, if the edge lies between a sample point and ...
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CAN Interrupt Handling The CAN controller has one interrupt output, which is connected with the interrupt controller unit in the C505C. This interrupt can be enabled/disabled using bit ECAN of SFR IEN1 (further details about interrupt vector, priority, etc. ...
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CAN Controller in Power Saving Modes Idle mode In the idle mode of the C505C the CAN controller is fully operable. When a CAN controller interrupt becomes active and the CAN controller interrupt is enabled, the C505C restarts, returns ...
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Configuration Examples of a Transmission Object The microcontroller wishes to configure an object for transmission. It wants to allow automatic transmission in response to remote frames but does not wish to receive interrupts for this object. Initialization: The identifier ...
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Configuration Examples of a Reception Object The microcontroller wishes to configure an object for reception. It wishes to receive an interrupt each time new data comes in. From time to time the microcontroller sends a remote request to trigger ...
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The CAN Application Interface The on-chip CAN controller of the C505C does not incorporate the physical layer that connects to the CAN bus. This must be provided externally. The module’s CAN controller is connected to this physical layer (ie. ...
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A/D Converter The C505 includes a high performance / high speed 8-bit A/D converter with 8 analog input channels. It operates with a successive approximation technique and provides the following features: – 8 multiplexed input channels (port 1), which ...
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IEN1 ( EXEN2 SWDT IRCON ( EXF2 TF2 P1ANA ( EAN6 EAN7 ADCON1 ( ADCL1 ADCL0 ADCON0 ( CLK Port 1 MUX Conversion f OSC Clock Prescaler V AREF ...
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A/D Converter Registers This section describes the bits/functions of the registers which are used by the A/D converter. Special Function Register ADDAT (Address Bit No. MSB This register holds the ...
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Special Function Register ADCON0 (Address Special Function Register ADCON1 (Address Bit No. MSB CLK DC H ADCL1 ADCL0 The shaded bits are not used for A/D converter control. Bit ...
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Bit Function ADCL1 A/D converter clock prescaler selection ADCL0 ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock f be adjusted in a way that the resulting conversion clock f than or equal to 1.25 MHz (see ...
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The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address Special Function Register IRCON (Address MSB Bit No ...
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A/D Converter Clock Selection The ADC uses two clock signals for operation : the conversion clock f clock f (1 derived from the C505 system clock ADC via the ADC clock prescaler as ...
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A/D Converter Timing An A/D conversion is started by writing into special function register ADST. A write-to-ADST will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle and ...
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Sample Time During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog input voltage to be converted. The analog voltage is internally fed to a voltage ...
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Depending on the selected prescaler ratio (see figure 6-43), two different relationships between machine cycles and A/D conversion are possible. The A/D conversion is always started with the beginning of a processor cycle when it has been started by writing ...
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Depending on the oscillator frequency of the C505 and the selected divider ratio of the conversion clock prescaler the total time of an A/D conversion is calculated according figure 6-44 and table 6-8. Figure 6-46 shows the minimum A/D conversion ...
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A/D Converter Analog Input Selection The analog inputs are located at port 1. The corresponding pins have a port structure, which allows to use them either as digital I/O pins or as analog inputs (see section 6.1.3.2). The analog ...
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Interrupt System The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the ...
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P3.2 / INT0 IT0 TCON Converter Timer 0 Overflow SWI IRCON.1 Status SIE CR.2 >1 Error EIE CR.3 Message Transmit >1 TXIE MCR0 Message Receive RXIE Bit addressable Request flag is cleared by hardware Figure ...
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P3.3 / INT1 IT1 TCON.2 P1.0 / AN0 / INT3 / CC0 I3FR T2CON.6 Timer 1 Overflow P1.1 / AN1 / INT4 / CC1 Bit addressable Request flag is cleared by hardware Figure 7-2 Interrupt Structure, Overview Part 2 Note: ...
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RI SCON.0 USART TI SCON.1 P1.2 / AN2 / INT5 / CC2 Timer 2 TF2 Overflow IRCON.6 P1.5 / AN5 / EXF2 T2EX EXEN2 IRCON.7 IEN1.7 P1.3 / INT6 / CC3 Bit addressable Request flag is cleared by hardware Figure ...
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Interrupt Registers 7.1.1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global disable bit (EA), ...
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The IEN1 register contains enable/disable flags of the timer 2 external timer reload interrupt, the external interrupts 2 and 3, the CAN controller interrupt and the A/D converter interrupt. Special Function Register IEN1 (Address MSB Bit No. ...
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Interrupt Request / Control Flags Special Function Register TCON (Address MSB Bit No TF1 TR1 The shaded bits are not used for interrupt control. Bit Function TF1 Timer 1 overflow ...
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Special Function Register T2CON (Address MSB Bit No T2PS I3FR The shaded bits are not used for interrupt control. Bit Function I3FR External interrupt 3 rising/falling edge control flag If I3FR = ...
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Special Function Register IRCON (Address MSB Bit No EXF2 TF2 Bit Function EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin ...
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The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the ...
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Special Function Register SCON (Address MSB Bit No SM0 SM1 The shaded bits are not used for interrupt control. Bit Function TI Serial interface transmitter interrupt flag Set by hardware at ...
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Interrupt Priority Registers The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in table 7-1 in the next section. Special Function Register IP0 (Address ...
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Interrupt Priority Level Structure The following table shows the interrupt grouping of the C505 interrupt sources. Table 7-1 Interrupt Source Structure Interrupt Associated Interrupts Group High priority 1 External interrupt 0 2 Timer 0 overflow 3 External interrupt 1 ...
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How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the ...
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Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-4 then, in accordance with the above rules, it will be vectored to during C5 and C6 ...
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External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit ITx ( 1), respectively in register TCON. If ITx = 0, external interrupt x ...
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Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active ...
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Fail Save Mechanisms The C505 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 192 approx. 412.5 ...
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Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C505. There is a prescaler available, which is software selectable and defines the input clock rate. This prescaler is controlled ...
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Watchdog Timer Control / Status Flags The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one status flag (located in SFR IP0). Special Function Register IEN0 (Address Special Function ...
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Starting the Watchdog Timer The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer an internal ...
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Refreshing the Watchdog Timer At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the watchdog cannot be stopped by software but can only be ...
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Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the ...
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EWPD WS (PCON1.7) (PCON1.4) P4.1 / RXDC Control P3.2 / INT0 Logic Start / Stop RC f Oscillator RC 3 MHz Start / XTAL1 Stop On-Chip XTAL2 Oscillator Figure 8-3 Functional Block Diagram of the Oscillator Watchdog The frequency coming ...
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This allows a reliable stabilization of the on chip oscillator. After that, the watchdog switches the clock supply back to the on-chip oscillator and releases the oscillator watchdog reset other ...
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Power Saving Modes The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode ...
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Special Function Register PCON1 (Mapped Address 88 H) Bit No. MSB EWPD – Symbol Function EWPD External wake-up from power down enable bit Setting EWPD before entering power down mode, enables the external wake- up from ...
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Idle Mode In the idle mode the oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the CAN controller (C505C only), ...
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The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE ...