ASM2I99456G-32-ER PULSECORE [PulseCore Semiconductor], ASM2I99456G-32-ER Datasheet

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ASM2I99456G-32-ER

Manufacturer Part Number
ASM2I99456G-32-ER
Description
3.3V/2.5V LVCMOS Clock Fanout Buffer
Manufacturer
PULSECORE [PulseCore Semiconductor]
Datasheet
November 2006
rev 0.3
Features
Functional Description
The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-Voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99456
offers 10 low-skew outputs and a differential LVPECL clock
input. The outputs are configurable and support 1:1 and 1:2
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
(150pS within one bank)
Configurable
distribution buffer
Compatible to single, dual and mixed 3.3V/2.5V
Voltage supply
Wide range output clock frequency up to
Designed for mid-range to high-performance
telecom, networking and computer applications
Supports high-performance differential clocking
applications
Max. output skew of 200pS
Selectable output configurations per output bank
Tristatable outputs
32 LQFP and TQFP Packages
Ambient Operating temperature range of
-40 to 85°C
Pin and Function compatible to MPC9456
250MHz
10
outputs
Notice: The information in this document is subject to change without notice.
3.3V/2.5V LVCMOS Clock Fanout Buffer
PulseCore Semiconductor Corporation
LVCMOS
www.pulsecoresemi.com
Clock
output to input frequency ratios. The ASM2I99456 is
specified for the extended temperature range of –40 to
85°C.
The ASM2I99456 is a full static design supporting clock
frequencies up to 250 MHz. The signals are generated and
retimed on-chip to ensure minimal skew between the three
output banks.
Each of the three output banks can be individually supplied
by 2.5V or 3.3V supporting mixed voltage applications. The
FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set
individually for each of the three output banks. The
ASM2I99456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. The clock input is
low voltage PECL compatible for differential clock
distribution support. Please consult the ASM2I99446
specification for a full CMOS compatible device. For series
terminated transmission lines, each of the ASM2I99456
outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a
7x7 mm
2
32-lead LQFP and TQFP Packages.
ASM2I99456

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ASM2I99456G-32-ER Summary of contents

Page 1

November 2006 rev 0.3 3.3V/2.5V LVCMOS Clock Fanout Buffer Features • Configurable 10 outputs distribution buffer • Compatible to single, dual and mixed 3.3V/2.5V Voltage supply • Wide range output clock frequency up to 250MHz • Designed for mid-range to ...

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November 2006 rev 0.3 Block Diagram PCLK 25K PCLK 25K FSELA 25K FSELB 25K FSELC 25K MR/OE 25K Pin Configuration VCCA QA2 GND QA1 VCCA QA0 GND MR/OE 3.3V/2.5V LVCMOS Clock Fanout Buffer Notice: The information in this document is ...

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November 2006 rev 0.3 Table 1. Pin Configuration Pin Number Pin PECL_CLK, 3 PECL_CLK 4 FSELA, FSELB, 5,6,7 FSELC 32 MR/OE 8,11,15,20,24,27,31 GND 25,29 VCCA, 1 18,22 VCCB , 9,13, 17 VCCC 2 VCC 30,28,26 QA0 - QA2 23,21,19 QB0 ...

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November 2006 rev 0.3 Table 5. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch–Up Immunity C Power Dissipation Capacitance PD Input Capacitance C IN Table 6. ...

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November 2006 rev 0.3 Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3V ± 5%, T Symbol Characteristics f Input Frequency ref Maximum Output f MAX Frequency V Peak-to-peak input voltage Common Mode ...

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November 2006 rev 0.3 Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T Symbol Characteristics Input Frequency f ref f Maximum Output Frequency MAX V Peak-to-peak input voltage Common Mode ...

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November 2006 rev 0.3 Driving Transmission Lines The ASM2I99456 clock driver was designed to drive high speed signals in a terminated transmission environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest ...

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November 2006 rev 0.3 Figure 3. Optimized Dual Line Termination Differential Z =50 0 Pulse Generator Ω Z= – Figure 4. PCLK ASM2I99456 AC Test Reference for VCC = 3.3V and VCC = 2.5V V ...

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November 2006 rev 0.3 Power Consumption of the ASM2I99456 and Thermal Management The ASM2I99456 AC specification is guaranteed for the entire operating frequency range up to 250MHz. The ASM2I99456 power consumption and the associated long-term reliability may decrease frequency limit, ...

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November 2006 rev 0.3 T ,MAX should be selected according to the MTBF J system requirements and Table 11. R thja from Table 12. The R represent data based on 1S2P thja boards, using 2S2P boards will result in a ...

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November 2006 rev 0.3 Package Information Symbol 3.3V/2.5V LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. ...

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November 2006 rev 0.3 Symbol 3.3V/2.5V LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 32-lead TQFP ...

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... Marking ASM2I99456G-32-LT ASM2I99456GL ASM2I99456G-32-LR ASM2I99456GL ASM2I99456G-32-ET ASM2I99456GE ASM2I99456G-32-ER ASM2I99456GE Device Ordering Information Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V/2.5V LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. Package Type 32-pin LQFP, Tray, Green 32-pin LQFP – ...

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November 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright ...

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