ST6200 STMICROELECTRONICS [STMicroelectronics], ST6200 Datasheet - Page 40

• Manufacturer Part Number: ST6200
• Description: 8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST6200C/ST6201C/ST6203C
I/O PORTS (Cont’d)
7.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
DRx with x = A or B.
Address DRA: 0C0h - Read /Write
Address DRB: 0C1h - Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register bits.
Reading the DR register returns either the DR reg-
ister latch content (pin configured as output) or the
digital value applied to the I/O pin (pin configured
as input).
Caution: In input mode, modifying this register will
modify the I/O port configuration (see
Do not use the Single bit instructions on I/O port
data registers. See
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A or B.
Address DDRA: 0C4h - Read /Write
Address DDRB: 0C5h - Read /Write
Reset Value: 0000 0000 (00h)
Table 10. I/O Port Register Map and Reset Values
40/100
1
DD7
D7
Address
of all I/O port registers
7
7
(Hex.)
0CCh
0CDh
0C0h
0C1h
0C4h
0C5h
Reset Value
DD6
D6
DRA
DRB
DDRA
DDRB
ORA
ORB
DD5
Register
D5
Label
(Section
DD4
D4
DD3
D3
MSB
MSB
MSB
7.2.5).
7
0
DD2
D2
Table
DD1
D1
6
0
8).
DD0
D0
0
0
5
0
Bit 7:0 = DD[7:0] Data direction register bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
ORx with x = A or B.
Address ORA: 0CCh - Read/Write
Address ORB: 0CDh - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0] Option register bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Output mode:
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
Input mode: See
Each bit is set and cleared by software.
Caution: Modifying this register, will also modify
the I/O port configuration in input mode. (see
ble
O7
7
8).
4
0
O6
O5
3
0
Table
O4
8.
2
0
O3
O2
1
0
O1
LSB
LSB
LSB
0
0
O0
0
Ta-