k9f6408q0c Samsung Semiconductor, Inc., k9f6408q0c Datasheet - Page 23

• Manufacturer Part Number: k9f6408q0c
• Description: 8m X 8 Bit Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

CLE
CE
WE
ALE
R/B
RE
I/O
K9F6408Q0C
K9F6408U0C
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred
to the data registers in less than 10 s(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B
pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to
low transitions of the RE clock output the data stating from the selected column address up to the last column address(column 511 or
527 depending on the state of GND input pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10 s again allows reading the selected page.The sequential row read operation is terminated by bringing CE high. The way
the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to
527 may be selectively accessed by writing the Read2 command with GND input pin low. Addresses A
of the spare area while addresses A
mented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1
command(00h/01h) is needed to move the pointer back to the main area. Figures 3 through 6 show typical sequence and timings for
each read operation.
Sequential Row Read is available only on K9F6408U0C_T,Q or K9F6408U0C_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 5, 6 show typical sequence and timings for sequential row read oper-
ation.
Figure 3. Read1 Operation
0
~
7
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half array (00h) at next cycle.
00h
01h
Start Add.(3Cycle)
A
0
~ A
7
4
& A
to A
9
~ A
7
22
are ignored. Unless the operation is aborted, the page address is automatically incre-
1st half array
t
R
(00h Command)
Data Field
2nd half array
23
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
Spare Field
Data Output(Sequential)
1st half array
FLASH MEMORY
(01h Command)*
Data Field
0
to A
3
2nd half array
set the starting address
Spare Field