k9k8g08u0m-y Samsung Semiconductor, Inc., k9k8g08u0m-y Datasheet - Page 7

• Manufacturer Part Number: k9k8g08u0m-y
• Description: 1g X 8 Bit / 2g X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PIN DESCRIPTION
NOTE : Connect all V
K9WAG08U1M
K9K8G08U0M
R/B / R/B1
Pin Name
I/O
CE / CE1
Do not leave V
0
CLE
CE2
ALE
Vcc
Vss
N.C
WE
WP
RE
~ I/O
7
CC
CC
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE / CE1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is
ignored, and the device does not return to standby mode in program or erase operation.
Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation.
CHIP ENABLE
The CE2 input enables the second K9K8G08U0M
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,
erase or random read operation is in process and returns to high state upon completion. It is an open drain
output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
POWER
V
GROUND
NO CONNECTION
Lead is not internally connected.
and V
CC
or V
is the power supply for device.
SS
SS
disconnected.
pins of each device to common power supply outputs.
7
Pin Function
FLASH MEMORY
Preliminary