FS6377-01 American Microsystems, Inc., FS6377-01 Datasheet - Page 2

• Manufacturer Part Number: FS6377-01
• Description: Programmable 3-pll Clock Generator ic
• Manufacturer: American Microsystems, Inc.

FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
DO = Digital Output; P = Power/Ground; # = Active Low pin
4.0
4.1
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired fre-
quency by a ratio of integers. This frequency multiplica-
tion is exact.
As shown in Figure 3, each PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscil-
lator (VCO), and a Feedback Divider.
During operation, the reference frequency (f
ated by the on-board crystal oscillator, is first reduced by
the Reference Divider. The divider value is called the
“modulus,” and is denoted as N
vider. The divided reference is then fed into the PFD.
The PFD controls the frequency of the VCO (f
through the charge pump and loop filter. The VCO pro-
vides a high-speed, low noise, continuously variable fre-
quency clock source for the PLL. The output of the VCO
is fed back to the PFD through the Feedback Divider (the
modulus is denoted by N
FS6377-01
FS6377-01
Programmable 3-PLL Clock Generator IC
Programmable 3-PLL Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Functional Block Description
Phase Locked Loops
TYPE
DI
DI
DI
AO
DI
DI
DO
DO
DO
DO
DI
AI
P
P
P
P
U
O
U
U
U
U
U
F
) to close the loop.
SEL_CD
CLK_D
CLK_C
CLK_B
CLK_A
NAME
ADDR
XOUT
VDD
VDD
SDA
VSS
VSS
SCL
XIN
PD
OE
R
for the Reference Di-
U
= Input with Internal Pull-Up; DI
Serial Interface Data Input/Output
Selects one of two PLL C, Mux C/D, and Post Divider C/D combinations
Power-Down Input
Ground
Crystal Oscillator Input
Output Enable Input
Power Supply (5V to 3.3V)
Address Select
D Clock Output
Ground
C Clock Output
B Clock Output
Power Supply (5V to 3.3V)
A Clock Output
Serial Interface Clock Input
Crystal Oscillator Output
REF
), gener-
VCO
)
2
Figure 3: PLL Diagram
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
f
REF
Reference
REFDIV[7:0]
Divider
(N
R
)
DESCRIPTION
f
PD
Frequency
f
Detector
Phase-
VCO
f
REF
Divider
Feedback
FBKDIV[10:0]
UP
DOWN
Charge
æ
ç ç
è
Pump
N
N
CP
(N
F
R
F
)
ö
÷ ÷
ø
.
Controlled
Oscillator
Voltage
Loop
Filter
LFTC
11.22.02
f
VCO