FS6051 American Microsystems, Inc., FS6051 Datasheet
FS6051
Related parts for FS6051
FS6051 Summary of contents
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... Serial interface I/O meet I C specifications; all other I/O are LVTTL/LVCMOS-compatible Five differerent pin configurations available: FS6050: 18 clock outputs in a 48-pin SSOP FS6051: 10 clock outputs in a 28-pin SOIC, SSOP FS6053: 13 clock outputs in a 28-pin SOIC FS6054: 14 clock outputs in a 28-pin SOIC Figure 1: Block Diagram (FS6050) VDD_I ...
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... Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Table 1: Pin Descriptions Key Analog Input Analog Output Digital Input Digital Output Power/Ground Active Low pin PIN (FS6050) PIN (FS6051) PIN (FS6053 ...
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... ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 3.2 Register Programming A logic-one written to a valid bit location turns on the as- signed output clock. Likewise, a logic-zero written to a valid bit location turns off the assigned output clock. Any unused or reserved register bits should be cleared to zero ...
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... OUTPUT PIN OUTPUT PIN (FS6051) (FS6053) - Pin 11 - Pin Pin 7 Pin 7 Pin 6 Pin 6 Pin 3 Pin 3 Pin 2 Pin 2 OUTPUT PIN OUTPUT PIN OUTPUT PIN (FS6051) (FS6053) Pin 27 Pin 27 Pin 26 Pin 26 Pin 23 Pin 23 Pin 22 Pin Pin 19 - Pin 18 OUTPUT PIN OUTPUT PIN OUTPUT PIN (FS6051) (FS6053) ...
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... ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 4.1.4 The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL C-bus) and the System line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs 2 For an I C-bus interface, the device can support two de- vice addresses to permit multiple devices on one I The A2 address bit is ignored and can be set to either a one or a zero ...
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... REGISTER ADDRESS 7-bit Receive Register Address Device Address Acknowledge START WRITE Command Command From bus host to device ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 2 C-bus) A DATA A P Data Acknowledge STOP Condition Acknowledge From device to bus host 2 C-bus DEVICE ADDRESS ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs 4.2.6 SMBus: Block Write The Block Write command permits the SMBus master to write several bytes of data to sequential registers, starting by default at Register 0. The ...
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... Table 8: Operating Conditions PARAMETER Supply Voltage, Clock Buffers Supply Voltage, Serial Communications Ambient Operating Temperature Range Input Frequency Output Load Capacitance Serial Data Transfer Rate ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 SYMBOL ) SYMBOL CONDITIONS/DESCRIPTION V 3.3V ± 3.3V ± 5% DD_I2C CLK ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Table 9: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits ...
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... Clock High Time * t Clock Low Time * t Duty Cycle * Tristate Enable Delay * Tristate Disable Delay * ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 CONDITIONS/DESCRIPTION Measured on the rising edge at 1.5V; t skw C = 20pF L Measured on the rising edge at 1.5V; PLH(min 20pF L Measured on the rising edge at 1.5V; PLH(max) ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Table 11: Serial Interface Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits ...
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... Figure 15: DC Measurement Points V = 2.4V OH 3.3 1. 0.4V OL 3.3 (device interface) Figure 16: Clock Skew Measurement Point 1.5V 3.3V t skw 3.3V 1.5V ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 High Drive Current (mA) Voltage (V) MIN. TYP. MAX. 0 -72 -116 -198 1 -72 -116 -198 1.4 -68 -110 -188 1.5 -67 -107 -184 1.65 -64 -103 -177 1 ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs 6.0 Package Information Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 ...
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... Table 15: 28-pin SOIC (7.5mm/0.300") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 28 AMERICAN MICROSYSTEMS, INC BASE PLANE SEATING PLANE SYMBOL CONDITIONS/DESCRIPTION Air flow = 0 m ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.068 0.078 1.73 2.00 A 0.002 ...
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... American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 OPERATING PACKAGE TYPE TEMPERATURE RANGE (Commercial (Commercial (Commercial (Commercial (Commercial) ...
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... FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs Low-Skew Clock Fanout Buffer ICs 8.0 Application Information 8.1 Reduction of EMI The primary concern when designing the board layout for this device is the reduction of electromagnetic interfer- ence (EMI) generated by the 18 copies of the 100MHz SDRAM clock ...
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... SCL lines depends on the supply voltage, the bus ca- ISO9001 ISO9001 ISO9001 ISO9001 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 FS6050/FS6051/FS6053/FS6054 pacitance, and the number of connected devices with their associated input currents. Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors on both lines. A guideline ...