74HC540D,652 NXP Semiconductors, 74HC540D,652 Datasheet - Page 11

• Manufacturer Part Number: 74HC540D,652
• Description: IC INVERTER 8-INPUT 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC540D,652

• Logic Type: Inverter
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Inputs: 8
• Number Of Circuits: 1
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: 74HC
• Number Of Channels Per Chip: 8
• Polarity: Inverting
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 7.8 mA
• Input Bias Current (max): 8 uA
• Low Level Output Current: 7.8 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 30 ns
• Number Of Lines (input / Output): 8 / 8
• Logical Function: Buffer/Line Driver
• Number Of Elements: 1
• Number Of Channels: 8
• Number Of Outputs: 8
• Operating Supply Voltage (typ): 5V
• Package Type: SO
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2V
• Quiescent Current: 8uA
• Technology: CMOS
• Pin Count: 20
• Mounting: Surface Mount
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2708-5; 933715490652

Philips Semiconductors
Test circuit for 74HC
AC waveforms 74HC (continued)
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
L
T
=
=
load capacitance including jig and probe capacitance
(see AC CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OFF-to-LOW
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
MGK562
OUTPUT
OUTPUT
OUTPUT
ENABLE
handbook, halfpage
GENERATOR
Fig.6 Propagation delays of 3-state outputs.
90%
PULSE
50%
t f
10%
t PLZ
enabled
outputs
t PHZ
Fig.5 Test circuit.
V I
10%
R T
90%
11
o
D.U.T
V CC
of
disabled
outputs
t r
V O
t PZL
t PZH
C L
FAMILY SPECIFICATIONS
MGK565
50%
50 pF
50%
outputs
enabled
V CC
GND