STV-5410-R01 STMICROELECTRONICS [STMicroelectronics], STV-5410-R01 Datasheet - Page 6

• Manufacturer Part Number: STV-5410-R01
• Description: Mono and Colour Digital Video CMOS Image Sensors
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

VV5410 & VV6410
2.3.1
Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the
video data stream to allow a co-processor to synchronise with video data the camera module is generating. Section 8. defines the
format for the output video data stream.
2.3.2
To complement the embedded control sequences the data qualification clock (QCK), the line start signal (LST) and the field start
signal (FST) signals can be independently set-up as follows:
There is also the choice of two different QCK frequencies where one is twice the frequency of the other.
2.3.3
The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses
are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written
to in parallel.
Section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed
via the serial interface.
1. Disabled
2. Free-running.
3. Qualify only the control sequences and the pixel data.
4. Qualify the pixel data only
1. Fast QCK: the falling edge of the clock qualifies every 8, 5 or 4 bit blocks of data that makes up a pixel value.
2. Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge quali-
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fies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode the rising edge of the clock qualifies the most signifi-
cant nibbles while the falling edge of the clock qualifies the least significant nibbles.
Digital Data Bus
Frame Grabber Control Signals
2-wire Serial Interface
RESETB
CLKI
Figure 1 : Block Diagram of VV5410/VV6410 Image Sensor (5-wire output)
AUDIO AMP.,
IMAGE
FORMAT
DECODER
VREGS,
& REFS
Y-
Commercial in confidence
cd5410-6410f-3-0.fm
CONTROL
EXPOSURE
Column ADC
X-Decoder
SRAM line store
PHOTO DIODE
ARRAY
OFFSET
CANCELLATION
INTERFACE
SERIAL
OUTPUT
Readout
Structure
FORMAT
Digital Logic
Analogue Core
D[4:0]
QCK
LST
FST
SDA
SCL
OEB
Introduction