CY28411OCT SPECTRALINEAR [SpectraLinear Inc], CY28411OCT Datasheet - Page 3

• Manufacturer Part Number: CY28411OCT
• Description: Clock Generator for Intel Alviso Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 22, 2006
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
Table 1. Frequency Select Table FS_A, FS_B and FS_C
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Table 2. Command Code Definition
Table 3. Block Read and Block Write Protocol
FS_C
MID
MID
MID
MID
27:20
18:11
(6:0)
0
0
0
0
1
1
1
8:2
Bit
Bit
10
19
1
9
7
FS_B
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
0
0
1
1
0
0
1
1
0
1
1
Block Write Protocol
FS_A
1
1
1
0
0
0
0
1
x
0
1
2
C_EN bit set)
Description
100 MHz
133 MHz
REF/2
REF/2
CPU
Hi-Z
100 MHz
100 MHz
REF/8
REF/8
SRC
Hi-Z
Description
PCIF/PCI
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
RESERVED
33 MHz
33 MHz
REF/24
REF/24
18:11
Hi-Z
Bit
8:2
10
19
20
1
9
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
14.318 MHz
14.318 MHz
REF0
REF
REF
Hi-Z
Block Read Protocol
Description
96 MHz
96 MHz
DOT96
REF
REF
Hi-Z
CY28411
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48 MHz
48 MHz
USB
REF
REF
Hi-Z