CY28410OC SPECTRALINEAR [SpectraLinear Inc], CY28410OC Datasheet - Page 4

• Manufacturer Part Number: CY28410OC
• Description: Clock Generator for Intel Grantsdale Chipset
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 21, 2006
Table 3. Block Read and Block Write Protocol (continued)
Table 4. Byte Read and Byte Write Protocol
Control Registers
Byte 0:Control Register 0
27:20
18:11
Bit
8:2
Bit
Bit
46
....
....
....
....
10
19
28
29
1
9
7
6
5
4
3
2
1
0
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
@Pup
1
1
1
1
1
1
1
1
Block Write Protocol
Byte Write Protocol
CPUC2_ITP/SRCC7
CPUT2_ITP/SRCT7
Description
Description
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
Reserved
Name
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved, Set = 1
46:39
55:48
18:11
27:21
37:30
Bit
38
47
56
....
....
....
....
Bit
8:2
10
19
20
28
29
38
39
1
9
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Start
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Slave address – 7 bits
Description
Block Read Protocol
Byte Read Protocol
Description
Description
CY28410
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