74AUP2G38GT,115 NXP Semiconductors, 74AUP2G38GT,115 Datasheet - Page 9

• Manufacturer Part Number: 74AUP2G38GT,115
• Description: IC NAND GATE DL 2-IN 8-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP2G38GT,115

• Number Of Circuits: 2
• Package / Case: 8-XSON
• Logic Type: NAND Gate with Open Drain
• Number Of Inputs: 2
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: AUP
• Low Level Output Current: 4 mA
• Propagation Delay Time: 19.5 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP2G38GT-G; 74AUP2G38GT-G; 935280716115

NXP Semiconductors
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
[2]
[3]
12. Waveforms
Table 9.
74AUP2G38
Product data sheet
Symbol
C
C
Supply voltage
V
0.8 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 3.6 V
Fig 8.
CC
L
PD
= 5 pF, 10 pF, 15 pF and 30 pF
All typical values are measured at nominal V
t
C
P
f
V
N = number of inputs switching.
pd
i
D
CC
PD
= input frequency in MHz;
is the same as t
= C
is used to determine the dynamic power dissipation (P
= supply voltage in V;
Measurement points are given in
Logic level V
The data input (nA, nB) to output (nY) propagation delays
PD
Parameter
power dissipation
capacitance
Dynamic characteristics
Measurement points
× V
CC
2
× f
PZL
OL
i
× N where:
is a typical output voltage level that occurs with the output load.
and t
PLZ
nA, nB input
Conditions
f = 1 MHz; V
.
nY output
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
Input
V
0.5V
0.5V
0.5V
…continued
= 0.8 V
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
M
Table
GND
V
V
CC
CC
CC
All information provided in this document is subject to legal disclaimers.
CC
OL
V
CC
I
I
= GND to V
9.
.
Rev. 5 — 23 September 2010
V
t
M
PLZ
D
CC
in μW).
V
X
[3]
Output
V
0.5V
0.5V
0.5V
Figure
Min
Low-power dual 2-input NAND gate; open drain
M
-
-
-
-
-
-
CC
CC
CC
Typ
9.
25 °C
t
PZL
0.6
0.7
0.8
0.9
1.1
1.4
[1]
V
Max
M
-
-
-
-
-
-
mnb132
Min
-
-
-
-
-
-
−40 °C to +125 °C
V
V
V
V
74AUP2G38
X
OL
OL
OL
(85 °C)
Max
+ 0.1 V
+ 0.15 V
+ 0.3 V
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
(125 °C)
Max
-
-
-
-
-
-
9 of 21
Unit
pF
pF
pF
pF
pF
pF