74AUP2G38GT,115 NXP Semiconductors, 74AUP2G38GT,115 Datasheet - Page 11

• Manufacturer Part Number: 74AUP2G38GT,115
• Description: IC NAND GATE DL 2-IN 8-XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP2G38GT,115

• Number Of Circuits: 2
• Package / Case: 8-XSON
• Logic Type: NAND Gate with Open Drain
• Number Of Inputs: 2
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: AUP
• Low Level Output Current: 4 mA
• Propagation Delay Time: 19.5 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP2G38GT-G; 74AUP2G38GT-G; 935280716115

NXP Semiconductors
13. Package outline
Fig 10. Package outline SOT765-1 (VSSOP8)
74AUP2G38
Product data sheet
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
UNIT
mm
VERSION
OUTLINE
SOT765-1
max.
A
1
0.15
0.00
A 1
8
1
Z
0.85
0.60
A 2
y
IEC
e
0.12
A 3
pin 1 index
D
0
0.27
0.17
b p
b p
All information provided in this document is subject to legal disclaimers.
MO-187
0.23
0.08
5
JEDEC
4
c
w
REFERENCES
Rev. 5 — 23 September 2010
D
2.1
1.9
M
(1)
E
2.4
2.2
(2)
c
JEITA
scale
2.5
0.5
e
A
H E
3.2
3.0
A 2
Low-power dual 2-input NAND gate; open drain
detail X
A 1
0.4
L
H E
E
0.40
0.15
L p
0.21
0.19
Q
5 mm
L
L p
PROJECTION
EUROPEAN
Q
0.2
v
A
(A 3 )
74AUP2G38
0.13
w
X
θ
v
M
0.1
y
© NXP B.V. 2010. All rights reserved.
A
ISSUE DATE
02-06-07
Z
0.4
0.1
(1)
SOT765-1
8°
0°
θ
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