CY28312B-2T SPECTRALINEAR [SpectraLinear Inc], CY28312B-2T Datasheet - Page 14

• Manufacturer Part Number: CY28312B-2T
• Manufacturer: SPECTRALINEAR [SpectraLinear Inc]

Rev 1.0, November 21, 2006
DC Electrical Characteristics
AC Electrical Characteristics
T
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
C
L
t
t
t
t
f
Z
t
t
t
t
t
t
t
t
t
f
Z
t
t
t
t
Note:
Parameter
R
F
D
JC
ST
Parameter
P
H
L
R
F
D
JC
SK
O
ST
Parameter
R
F
D
JC
A
6. Refer to Figure 1 for K7 operation clock driver test circuit.
Parameter
IN
o
o
OUT
= 0°C to +70°C, V
Period
High Time
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Output Skew
CPU to PCI Clock Skew
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle-to-Cycle
Output Rise Edge Rate CPU_CS
Output Fall Edge Rate
Duty Cycle
Jitter, Cycle to Cycle
Frequency Stabilization
from Power-up (cold
start)
AC Output Impedance
Output Pin Capacitance
Input Pin Inductance
Description
Description
Description
DDQ3
= 3.3V±5%, f
Description
T
CPU_CS
Measured at 50% point
Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
V
A
XTL
O
Measured from 2.0V to 0.8V
Measured on rising edge at 1.5V. Maximum difference
Measured on rising edge at 1.5V
Measured on rising edge at 1.5V. Maximum difference
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.8V to 2.0V
Measured on rising and falling edge at 1.5V
of cycle time between two adjacent cycles.
Covers all CPU/PCI outputs. Measured on rising edge
at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Average value during switching transition. Used for
determining series termination value.
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured at 1.5V
of cycle time between two adjacent cycles.
= 0°C to +70°C, V
= V
= 14.31818 MHz
Test Condition/Comments
X
[6]
Test Condition/Comments
Test Condition/Comments
DD
Test Condition
= 3.3V ± 5% and 2.5V ± 5% (continued)
Min. Typ. Max.
1.0
1.0
CPU = 100 MHz
45
50
Min.
3
250
4.0
4.0
55
Min.
Min.
1.5
0.5
0.5
30
12
12
45
45
Typ.
1
1
Min.
1.0
1.0
CPU = 133 MHz
45
CY28312B-2
Typ.
Typ.
30
Typ. Max.
Max.
50
3
6
7
Page 14 of 17
Max.
Max.
250
500
250
2.0
2.0
55
55
4
4
4
3
250
4.0
4.0
55
Unit
nH
pF
V/ns
V/ns
V/ns
V/ns
Unit
Unit
Unit
V/ns
V/ns
ms
ns
ns
ns
ps
ps
ns
ps
ms
%
%
ps
%
W