CY2833 CYPRESS [Cypress Semiconductor], CY2833 Datasheet - Page 5
![no-image](/images/no-image-200.jpg)
CY2833
Manufacturer Part Number
CY2833
Description
Intel CK408 Mobile Clock Synthesizer
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY2833.pdf
(18 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY283300C
Manufacturer:
CY
Quantity:
32 799
Part Number:
CY283310C
Manufacturer:
CYP
Quantity:
20 000
Company:
Part Number:
CY283310C-11
Manufacturer:
NS
Quantity:
2 286
Company:
Part Number:
CY283310C-2
Manufacturer:
CY
Quantity:
2 037
Part Number:
CY283310CT
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY283310XCT
Manufacturer:
CYP
Quantity:
20 000
Part Number:
CY28331OCT
Manufacturer:
CYP
Quantity:
20 000
Part Number:
CY28331OXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-07507 Rev. *A
Byte 6: Silicon Signature Register
Byte 7: Reserved Register
Byte 8: Dial-a-Frequency Control Register N
Byte 9: Dial-a-Frequency Control Register R
Note:
5.
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
@Pup
@Pup
@Pup
@Pup
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
N6, MSB
N5
N4
N3
N2
N3
N0, LSB
R5, MSB
R4
R3
R2
R1
R0
DAF_ENB
Name
Name
Name
[5]
Name
(all bits are Read-only)
Revision = 0001
Vendor Code = 0011
Reserved. Set = 0.
These bits are for programming the PLL’s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that are
generated from the same PLL, such as PCI) remain at their existing
ratios relative to the CPU clock.
Reserved. Set = 0.
These bits are for programming the PLL’s internal R register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that are
generated from the same PLL, such as PCI) remain at their existing
ratios relative to the CPU clock.
R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is loaded from DAF (SMBus) registers.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Reserved. Set = 0.
Description
Description
Description
Description
CY28339
Page 5 of 18