PLL701-10 PhaseLink (PLL), PLL701-10 Datasheet - Page 4

• Manufacturer Part Number: PLL701-10
• Description: , 1x to 8x Out, 15-30MHz In, 15-240MHz Out, SST
• Manufacturer: PhaseLink (PLL)

PLL701-10
Preliminary
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and modulation rates
The PLL701-10 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation, as well as
selectable modulation rate. Selection is made by connecting specific input pins to a logical “zero” or “one”. Pins 6
(SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation as shown on
the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as inputs to select the output
frequency as shown on the output clock selection table (page 1). Pin 11 is the output enable pin, that tri-states all
outputs when low (logical “zero”).
In order to reduce the number of pins on the chip, the PLL701-10 uses pin 2 and 14 (XOUT/SD0 and REF/SD1) as
a bi-directional pin. The pins serve as modulation rate selector inputs (SD0 and SD1) upon power-up (see
modulation rate table on page 1), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon
as the inputs have been latched.
Connecting a selection pin to a logical “one”
All selection pins have an internal pull-up resistor (30k
for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120k
for pin 2).
This internal pull-up resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive
load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a
logical “one” upon power-up.
Connecting a selection pin to a logical “zero”
For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be
grounded to pull the input down to a logical “zero”. Connecting the bi-directional pins (SD0 and SD1) to a logical
“zero” will however require the use of an external loading resistor between the pin and GND that has to be
sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical
“zero”). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor
should however be kept as large as possible. In general, it is recommended to use an external resistor of around
Rup/4 (e.g. 27k
for pin 2 and 4.7k
for pin 14, see Application Diagram).
APPLICATION DIAGRAM FOR OUTPUT AND MODULATION SELECTION
Internal to chip
External Circuitry
VDD
R
up
R
Power Up
Reset
RB
Clock Load
Bi-directional pin
XIN
EN
R
/4
SD0 or
up
Latch
SC0~SC2
Jumper
options
NOTE: Rup=120k
for SD0 (Pin2); and Rup=30k
for SD1(Pin 14). R starts from 1 to 0 while RB starts from 0 to 1.
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Rev 11/04/02 Page 4