CY2308-1 CYPRESS [Cypress Semiconductor], CY2308-1 Datasheet

CY2308-1

Manufacturer Part Number

CY2308-1

Description

3.3V Zero Delay Buffer

Manufacturer

CYPRESS [Cypress Semiconductor]

Datasheet

1.CY2308-1.pdf (15 pages)

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Cypress Semiconductor Corporation

Document Number: 38-07146 Rev. *E

Features

■

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip PLL that locks to an input clock

presented on the REF pin. The PLL feedback is driven into the

FBK pin and obtained from one of the outputs. The

input-to-output skew is less than 350 ps and output-to-output

skew is less than 200 ps.

The CY2308 has two banks of four outputs each that is

controlled by the Select inputs as shown in the table

Logic Block Diagram

Zero input-output propagation delay, adjustable by

capacitive load on FBK input

Multiple configurations, see

tions”

Multiple low skew outputs

Two banks of four outputs, three-stateable by two select

inputs

10 MHz to 133 MHz operating range

75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP

3.3V operation

Industrial Temperature available

on page 3

REF

“Available CY2308 Configura-

Extra Divider (–5H)

Extra Divider (–3, –4)

•

Extra Divider (–2, –3)

198 Champion Court

Select Input

Decoding

PLL

“Select

MUX

Input Decoding”

required, Bank B is three-stated. The input clock is directly

applied to the output for chip and system testing purposes by

the select inputs.

The CY2308 PLL enters a power down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off resulting in less than

50 μA of current draw. The PLL shuts down in two additional

cases as shown in the table

page 2.

Multiple CY2308 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

The CY2308 is available in five different configurations as

shown in the table

page 3. The CY2308–1 is the base part where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high drive version of the

–1 and rise and fall times on this device are much faster.

The CY2308–2 enables the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depend on the output that drives the

feedback pin. The CY2308–3 enables the user to obtain 4X

and 2X frequencies on the outputs.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile and is used in a

variety of applications.

The CY2308–5H is a high drive version with REF/2 on both

banks.

•

San Jose

3.3V Zero Delay Buffer

on page

“Available CY2308 Configurations”

CA 95134-1709

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

2”.

If all output clocks are not

“Select Input Decoding”

Revised August 03, 2007

•

408-943-2600

CY2308

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Related parts for CY2308-1

CY2308-1 Summary of contents

Page 1

... The CY2308–3 enables the user to obtain 4X and 2X frequencies on the outputs. The CY2308–4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile and is used in a variety of applications. ...

Page 2

... Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input CLOCK B1–B4 Tri-State Tri-State [4] [4] Driven Driven CY2308 Output Source PLL Shutdown PLL Y PLL N Reference Y PLL N Page [+] Feedback ...

Page 3

... Table 2. For applications requiring zero input-output delay, all outputs including the one providing feedback is equally loaded. Note 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2. Document Number: 38-07146 Rev. *E Bank A Frequency Reference Reference ...

Page 4

... –12 mA (–1H, –5H) OH Unloaded outputs, 100 MHz REF, Select inputs GND DD Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) Unloaded outputs, 33 MHz REF (–1, –2, –3, –4) CY2308 Min Max Unit 3.0 3 °C – – ...

Page 5

... PLL Lock Time LOCK Notes 8. All parameters are specified with loaded outputs. 9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz. Document Number: 38-07146 Rev. *E Test Conditions 30-pF load, All devices [9] 20-pF load, –1H, –5H devices 15-pF load, –1, –2, –3, –4 devices Measured at 1 ...

Page 6

... –12 mA (–1H, –5H) OH REF = 0 MHz Unloaded outputs, 100 MHz, Select inputs GND DD Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) Unloaded outputs, 66 MHz REF (–1, –2, –3, –4) CY2308 Min Max Unit 3.0 3.6 V –40 85 °C – – ...

Page 7

... Measured at 66.67 MHz, loaded outputs load Measured at 133.3 MHz, loaded outputs load Measured at 66.67 MHz, loaded outputs 30 pF load Measured at 66.67 MHz, loaded outputs 15 pF load Stable power supply, valid clocks presented on REF and FBK pins CY2308 [8] Min Typ Max Unit 10 – 100 MHz 10 – ...

Page 8

... FBK t 6 FBK, Device 1 FBK, Device 2 t Document Number: 38-07146 Rev. *E Figure 2. Duty Cycle Timing 1.4V 1.4V Figure 3. All Outputs Rise/Fall Time 2.0V 0. Figure 4. Output-Output Skew 1.4V Figure 5. Input-Output Propagation Delay Figure 6. Device-Device Skew CY2308 3.3V 0V Page [+] Feedback ...

Page 9

... I data is calculated from nCVf, where CORE (n = number of outputs Capacitance load per output (F Voltage Supply (V frequency (Hz). Document Number: 38-07146 Rev. *E Trends [11] for CY2308–1,2,3,4 (for 15 pF Loads over Frequency - 3.3V, 25C MHz 52 66 MHz 50 100 MHz ...

Page 10

... Loads over Frequency - 3.3V, 25C) 140 120 100 Document Number: 38-07146 Rev. *E Trends [11] for CY2308–1H, 5H (for 15 pF Loads over Frequency - 3.3V, 25C MHz 66 MHz 50 100 MHz 3 ...

Page 11

... Test Circuit for all parameters except t Document Number: 38-07146 Rev. *E Test Circuit 0.1 μF CLK OUT C LOAD V DD 0.1 μF GND Test Circuit for t , Output slew rate on –1H, –5 device 8 8 CY2308 1 KΩ CLK out Outputs 1 KΩ GND Page [+] Feedback ...

Page 12

... SOIC - Tape and Reel CY2308SXI–1 16-pin 150 mil SOIC CY2308SXI–1T 16-pin 150 mil SOIC - Tape and Reel CY2308SXC–1H 16-pin 150 mil SOIC CY2308SXC–1HT 16-pin 150 mil SOIC - Tape and Reel CY2308SXI–1H 16-pin 150 mil SOIC CY2308SXI– ...

Page 13

... SOIC CY2308SXI–4T 16-pin 150 mil SOIC - Tape and Reel CY2308SXC–5H 16-pin 150 mil SOIC CY2308SXC–5HT 16-pin 150 mil SOIC - Tape and Reel CY2308SXI–5H 16-pin 150 mil SOIC CY2308SXI–5HT 16-pin 150 mil SOIC - Tape and Reel Document Number: 38-07146 Rev ...

Page 14

... Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY2308 MAX. PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.016[0.406] 0.0098[0.249] 0.035[0.889] 51-85068-*B MAX ...

Page 15

... Document History Page Document Title: CY2308 3.3V Zero Delay Buffer Document Number: 38-07146 Orig. of REV. ECN NO. Issue Date Change ** 110255 12/17/01 SZV *A 118722 10/31/02 RGL *B 121832 12/14/02 *C 235854 See ECN RGL *D 310594 See ECN RGL *E 1344343 See ECN KVM/VED Brought the Ordering Information Table up to date: removed three obsolete parts © ...

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