BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 41

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

BS85B12-3/BS85C20-3
Touch Key Flash MCU with LCD/LED Driver
Rev. 1.00
Bit 7~5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
R/W
POR
Control Register
Bit
SMOD Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
CKS2
R/W
CKS2~CKS0: The system clock selection when HLCLK is 0
These three bits are used to select which clock is used as the system clock source. In addition
to the system clock source, which is LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Undefined bit
These bits can be read or written by user software program.
LTO: Low speed system oscillator ready flag
This is the low speed system oscillator ready flag which indicates when the low speed system
oscillator is stable after power on reset.
HTO: High speed system oscillator ready flag
This is the high speed system oscillator ready flag which indicates when the high speed system
oscillator is stable. This flag is cleared to 0 by hardware when the device is powered on and
then changes to a high level after the high speed system oscillator is stable. Therefore this flag
will always be read as 1 by the application program after device power-on. The flag will be
low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to
a high level after 15~16 clock cycles.
IDLEN: IDLE Mode control
This is the IDLE Mode Control bit and determines what happens when the HALT instruction is
executed. If this bit is high, when a HALT instruction is executed the device will enter the
IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to
keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU
and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the
SLEEP Mode when a HALT instruction is executed.
HLCLK: system clock selection
This bit is used to select if the f
clock. When the bit is high the f
be selected. When system clock switches from the f
be automatically switched off to conserve power.
7
0
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
0: not ready
1: ready
0: not ready
1: ready
0: disable
1: enable
0: f
1: f
H
H
/2 ~ f
H
H
H
L
L
H
H
H
/2
/32
/4
/64
/16
/8
(f
(f
LIRC
LIRC
H
CKS1
/64 or f
R/W
)
)
6
0
L
CKS0
R/W
5
0
H
H
clock or the f
clock will be selected and if low the f
R/W
D4
35
4
0
H
/2 ~ f
LTO
H
R
3
0
/64 or f
H
clock to the f
L
clock is used as the system
HTO
R
2
0
L
clock and the f
H
/2 ~ f
IDLEN
H
R/W
/64 or f
1
1
February 1, 2011
H
L
clock will
clock will
HLCLK
R/W
0
1